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| author | Arthur Heymans <arthur@aheymans.xyz> | 2021-05-29 07:30:33 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-06-07 12:54:39 +0000 |
| commit | bab9e2e6bdf3bbfa6047773a04632e0fbdf64afb (patch) | |
| tree | ab42496f77d4bf76f3f9f79eea16ddc92d8a5cd6 /src/soc/amd/picasso | |
| parent | 11cac784ff788b4f0495758d7f5992e457ea552c (diff) | |
| download | coreboot-bab9e2e6bdf3bbfa6047773a04632e0fbdf64afb.tar.gz coreboot-bab9e2e6bdf3bbfa6047773a04632e0fbdf64afb.tar.bz2 coreboot-bab9e2e6bdf3bbfa6047773a04632e0fbdf64afb.zip | |
arch/x86: Add a common romstage entry
It might be possible to have this used for more than x86, but that
will be for a later commit.
Change-Id: I4968364a95b5c69c21d3915d302d23e6f1ca182f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Diffstat (limited to 'src/soc/amd/picasso')
| -rw-r--r-- | src/soc/amd/picasso/romstage.c | 11 |
1 files changed, 3 insertions, 8 deletions
diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index 359eacf4b7ac..e66f423d52ad 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -8,19 +8,13 @@ #include <console/console.h> #include <fsp/api.h> #include <program_loading.h> -#include <timestamp.h> +#include <romstage_common.h> #include <types.h> -asmlinkage void car_stage_entry(void) +void __noreturn romstage_main(void) { - timestamp_add_now(TS_ROMSTAGE_START); - post_code(0x40); - console_init(); - - post_code(0x42); - /* Snapshot chipset state prior to any FSP call. */ fill_chipset_state(); @@ -33,4 +27,5 @@ asmlinkage void car_stage_entry(void) run_ramstage(); post_code(0x50); /* Should never see this post code. */ + die("failed to load ramstage\n"); } |