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| author | Felix Held <felix-coreboot@felixheld.de> | 2022-06-10 21:04:36 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-06-13 15:53:32 +0000 |
| commit | a05f518dea5fe700d99dcce1882739a15427a0d9 (patch) | |
| tree | 499b3d6d021987e165a61a6429b371942bd1e002 /src/soc/amd/sabrina/include | |
| parent | 868282e195dd8700d0e3d2a26ba7295f21a15f56 (diff) | |
| download | coreboot-a05f518dea5fe700d99dcce1882739a15427a0d9.tar.gz coreboot-a05f518dea5fe700d99dcce1882739a15427a0d9.tar.bz2 coreboot-a05f518dea5fe700d99dcce1882739a15427a0d9.zip | |
soc/amd/sabrina: only make the available clock outputs configurable
Sabrina only has 4 PCIe clock outputs with corresponding clock request
pins available, so only make those 4 configurable in devicetree and
disable the rest unconditionally.
TEST=None
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5d34fa680dd20a6eec86cc278c1c901b3231df83
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65089
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc/amd/sabrina/include')
| -rw-r--r-- | src/soc/amd/sabrina/include/soc/southbridge.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/amd/sabrina/include/soc/southbridge.h b/src/soc/amd/sabrina/include/soc/southbridge.h index e755d5019caf..d72696285d36 100644 --- a/src/soc/amd/sabrina/include/soc/southbridge.h +++ b/src/soc/amd/sabrina/include/soc/southbridge.h @@ -96,6 +96,7 @@ #define GPP_CLK5_REQ_SHIFT 10 #define GPP_CLK6_REQ_SHIFT 12 #define GPP_CLK_OUTPUT_COUNT 7 +#define GPP_CLK_OUTPUT_AVAILABLE 4 #define GPP_CLK_REQ_MASK(clk_shift) (0x3 << (clk_shift)) #define GPP_CLK_REQ_ON(clk_shift) (0x3 << (clk_shift)) #define GPP_CLK_REQ_EXT(clk_shift) (0x1 << (clk_shift)) |