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| author | Karthikeyan Ramasubramanian <kramasub@google.com> | 2022-07-14 17:29:06 -0600 |
|---|---|---|
| committer | Martin L Roth <gaumless@tutanota.com> | 2022-07-20 14:15:55 +0000 |
| commit | 8ebb04c257b1f37ed853dbe9ead2f2ea59977ed5 (patch) | |
| tree | f1fc99571a5a063f45e5186e8e08eb14cd4aac00 /src/soc/amd/sabrina | |
| parent | e3eedf7548f282549d272d4e9b352dfb6e3b80da (diff) | |
| download | coreboot-8ebb04c257b1f37ed853dbe9ead2f2ea59977ed5.tar.gz coreboot-8ebb04c257b1f37ed853dbe9ead2f2ea59977ed5.tar.bz2 coreboot-8ebb04c257b1f37ed853dbe9ead2f2ea59977ed5.zip | |
soc/amd/sabrina: Fix boot region address passed to PSP
PSP expects PSP L2 directory address relative to the start of the SPI
ROM. Also PSP does not expect BIOS L2 directory address since it is an
entry in PSP L2 directory. Update the configuration such that PSP
verstage passes the right address to PSP.
BUG=b:217414563
TEST=Build Skyrim BIOS image. Ensure that PSP verstage passes the
address as expected by PSP.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I8dc3aa4cb401d16a68da446f83eb9e68ee290fea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65866
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc/amd/sabrina')
| -rw-r--r-- | src/soc/amd/sabrina/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/amd/sabrina/psp_verstage/chipset.c | 2 |
2 files changed, 2 insertions, 1 deletions
diff --git a/src/soc/amd/sabrina/Kconfig b/src/soc/amd/sabrina/Kconfig index 515eca7b1b7d..b67d76977a60 100644 --- a/src/soc/amd/sabrina/Kconfig +++ b/src/soc/amd/sabrina/Kconfig @@ -45,6 +45,7 @@ config SOC_SPECIFIC_OPTIONS select PLATFORM_USES_FSP2_0 select PROVIDES_ROM_SHARING select PSP_VERSTAGE_CCP_DMA if VBOOT_STARTS_BEFORE_BOOTBLOCK + select PSP_SUPPORTS_EFS2_RELATIVE_ADDR if VBOOT_STARTS_BEFORE_BOOTBLOCK select RESET_VECTOR_IN_RAM select RTC select SOC_AMD_COMMON diff --git a/src/soc/amd/sabrina/psp_verstage/chipset.c b/src/soc/amd/sabrina/psp_verstage/chipset.c index 7f86dbfebf8e..d4a33f0832d8 100644 --- a/src/soc/amd/sabrina/psp_verstage/chipset.c +++ b/src/soc/amd/sabrina/psp_verstage/chipset.c @@ -18,7 +18,7 @@ uint32_t save_uapp_data(void *address, uint32_t size) uint32_t get_bios_dir_addr(struct embedded_firmware *ef_table) { - return ef_table->bios3_entry; + return 0; } int platform_set_sha_op(enum vb2_hash_algorithm hash_alg, |