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| author | Karthikeyan Ramasubramanian <kramasub@google.com> | 2022-07-14 15:37:07 -0600 |
|---|---|---|
| committer | Martin L Roth <gaumless@tutanota.com> | 2022-07-20 14:14:30 +0000 |
| commit | e3eedf7548f282549d272d4e9b352dfb6e3b80da (patch) | |
| tree | d0eb32dd51d04b13b4fd5f3c0c5c7a1e2e8ad33b /src/soc/amd/sabrina | |
| parent | df74de1cac679549b515ed5f4eb86e7229ab53cc (diff) | |
| download | coreboot-e3eedf7548f282549d272d4e9b352dfb6e3b80da.tar.gz coreboot-e3eedf7548f282549d272d4e9b352dfb6e3b80da.tar.bz2 coreboot-e3eedf7548f282549d272d4e9b352dfb6e3b80da.zip | |
soc/amd/common/psp_verstage: Fix update_boot_region
On SoCs where PSP use A/B recovery layout, PSP expects PSP L2 directory
address relative to the start of the SPI ROM. Unfortunately there is
nothing in the EFS2 header to help identify such SoCs. Hence add a
config item to statically identify such SoCs.
Also when PSP uses A/B recovery layout, BIOS L2 directory is an entry in
the PSP L2 directory. Hence the address of BIOS L2 directory is not part
of EFS2 header. Thankfully PSP is able to identify the BIOS L2 directory
itself and does not expect PSP verstage to pass the address. Modify PSP
verstage to handle these updates.
BUG=b:217414563
TEST=Build Skyrim BIOS image. Ensure that PSP verstage returned the PSP
L2 directory as expected.
Change-Id: I2f856a62055c80b8e2db91c983832611a5f0389c
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc/amd/sabrina')
0 files changed, 0 insertions, 0 deletions