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| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2019-05-01 16:14:42 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2019-05-08 13:48:31 +0000 |
| commit | 5de4771360c0e57bd76bc81850298091e0b9bde7 (patch) | |
| tree | 52d921e282de61c13f662d27165bd7a846414ed8 /src/soc/amd/stoneyridge/include/soc/iomap.h | |
| parent | fe80bf2fd1e4f027d68af1c5bc58a8b1344a806d (diff) | |
| download | coreboot-5de4771360c0e57bd76bc81850298091e0b9bde7.tar.gz coreboot-5de4771360c0e57bd76bc81850298091e0b9bde7.tar.bz2 coreboot-5de4771360c0e57bd76bc81850298091e0b9bde7.zip | |
soc/amd/stoneyridge: Rename AcpiMmio blocks
A subsequent patch will move the AcpiMmio support into amd/common.
Take this opportunity to rename the blocks in the 0xfed8xxxx region
with more consistency.
Change-Id: I9a69a6ecfc10f78b4860df05a77a061d2fc8be7d
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/amd/stoneyridge/include/soc/iomap.h')
| -rw-r--r-- | src/soc/amd/stoneyridge/include/soc/iomap.h | 34 |
1 files changed, 22 insertions, 12 deletions
diff --git a/src/soc/amd/stoneyridge/include/soc/iomap.h b/src/soc/amd/stoneyridge/include/soc/iomap.h index 613dd044f602..e6327dc6db61 100644 --- a/src/soc/amd/stoneyridge/include/soc/iomap.h +++ b/src/soc/amd/stoneyridge/include/soc/iomap.h @@ -32,19 +32,29 @@ #endif #define HPET_BASE_ADDRESS 0xfed00000 -/* Register blocks at fixed offsets from FED8_0000h and enabled in PMx04[1] */ +/* AcpiMmio blocks are at fixed offsets from FED8_0000h, enabled in PMx04[1] */ #define AMD_SB_ACPI_MMIO_ADDR 0xfed80000 -#define APU_SMI_BASE 0xfed80200 -#define PM_MMIO_BASE 0xfed80300 -#define BIOSRAM_MMIO_BASE 0xfed80500 -#define ACPI_REG_MMIO_BASE 0xfed80800 -#define ASF_MMIO_BASE 0xfed80900 -#define SMBUS_MMIO_BASE 0xfed80a00 -#define GPIO_IOMUX_MMIO_BASE 0xfed80d00 -#define MISC_MMIO_BASE 0xfed80e00 -#define XHCI_ACPI_PM_MMIO_BASE 0xfed81c00 -#define GPIO_CONTROL_MMIO_BASE 0xfed81500 -#define AOAC_MMIO_BASE 0xfed81e00 +#define ACPIMMIO_SM_PCI_BASE 0xfed80000 +#define ACPIMMIO_SMI_BASE 0xfed80200 +#define ACPIMMIO_PMIO_BASE 0xfed80300 +#define ACPIMMIO_PMIO2_BASE 0xfed80400 +#define ACPIMMIO_BIOSRAM_BASE 0xfed80500 +#define ACPIMMIO_CMOSRAM_BASE 0xfed80600 +#define ACPIMMIO_CMOS_BASE 0xfed80700 +#define ACPIMMIO_ACPI_BASE 0xfed80800 +#define ACPIMMIO_ASF_BASE 0xfed80900 +#define ACPIMMIO_SMBUS_BASE 0xfed80a00 +#define ACPIMMIO_WDT_BASE 0xfed80b00 +#define ACPIMMIO_HPET_BASE 0xfed80c00 +#define ACPIMMIO_IOMUX_BASE 0xfed80d00 +#define ACPIMMIO_MISC_BASE 0xfed80e00 +#define ACPIMMIO_DPVGA_BASE 0xfed81400 +#define ACPIMMIO_GPIO0_BASE 0xfed81500 +#define ACPIMMIO_GPIO1_BASE 0xfed81600 +#define ACPIMMIO_GPIO2_BASE 0xfed81700 +#define ACPIMMIO_XHCIPM_BASE 0xfed81c00 +#define ACPIMMIO_ACDCTMR_BASE 0xfed81d00 +#define ACPIMMIO_AOAC_BASE 0xfed81e00 #define APU_UART0_BASE 0xfedc6000 #define APU_UART1_BASE 0xfedc8000 |