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authorMarc Jones <marcj303@gmail.com>2017-05-04 21:17:45 -0600
committerMartin Roth <martinroth@google.com>2017-06-26 00:45:41 +0000
commit244848462def7075e0c812a2f71c408668cacfe4 (patch)
treefde926f45d478b36eaebfd1261886c973b803857 /src/soc/amd/stoneyridge/reset.c
parenta0199d8e1a96d94828b31f77e0a29a282871a76a (diff)
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soc: Add AMD Stoney Ridge southbridge code
Copy the Hudson/Kern code from southbridge/amd/pi/hudson. This is the first of a series of patches to migrate Stoney Ridge support from cpu, northbridge, and southbridge to soc/ Changes: - add soc/amd/stoneyridge and soc/amd/common - remove all other Husdon versions - update include paths, etc - clean up Kconfig and Makefile - create chip.c to contain chip_ops Change-Id: Ib88a868e654ad127be70ecc506f6b90b784f8d1b Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/amd/stoneyridge/reset.c')
-rw-r--r--src/soc/amd/stoneyridge/reset.c45
1 files changed, 45 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/reset.c b/src/soc/amd/stoneyridge/reset.c
new file mode 100644
index 000000000000..e44a88638263
--- /dev/null
+++ b/src/soc/amd/stoneyridge/reset.c
@@ -0,0 +1,45 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+// Use simple device model for this file even in ramstage
+#define __SIMPLE_DEVICE__
+
+#include <arch/io.h>
+#include <reset.h>
+
+#define HT_INIT_CONTROL 0x6C
+ #define HTIC_BIOSR_Detect (1 << 5)
+
+
+static void set_bios_reset(void)
+{
+ u32 htic;
+ htic = pci_io_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL);
+ htic &= ~HTIC_BIOSR_Detect;
+ pci_io_write_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL, htic);
+}
+
+void do_hard_reset(void)
+{
+ set_bios_reset();
+ /* Try rebooting through port 0xcf9 */
+ /*
+ * Actually it is not a real hard_reset
+ * --- it only reset coherent link table,
+ * but not reset link freq and width
+ */
+ outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9);
+ outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9);
+}