| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | soc/amd/stoneyridge/reset: use port and bit defines from cf9_reset.h | Felix Held | 2020-12-10 | 1 | -2/+3 |
| * | treewide: Remove "this file is part of" lines | Patrick Georgi | 2020-05-11 | 1 | -1/+0 |
| * | soc/amd: Use SPDX for GPL-2.0-only files | Angel Pons | 2020-04-05 | 1 | -13/+2 |
| * | soc: Remove copyright notices | Patrick Georgi | 2020-03-18 | 1 | -2/+0 |
| * | soc/amd/common: Create AcpiMmio functionality from stoneyridge | Marshall Dawson | 2019-05-16 | 1 | -0/+1 |
| * | soc/amd: Implement common reset API | Nico Huber | 2018-10-22 | 1 | -2/+9 |
| * | amd/stoneyridge: Add warm reset detection | Marshall Dawson | 2018-08-08 | 1 | -0/+16 |
| * | pci: Move inline PCI functions to pci_ops.h | Patrick Rudolph | 2018-04-20 | 1 | -0/+1 |
| * | soc/amd/stoney: clean up and update reset.c | Martin Roth | 2017-12-01 | 1 | -20/+22 |
| * | stoneyridge: Rename hudson to southbridge | Marc Jones | 2017-08-14 | 1 | -1/+1 |
| * | soc/amd/stoneyridge: Fix most checkpatch errors | Marshall Dawson | 2017-06-27 | 1 | -3/+4 |
| * | soc: Add AMD Stoney Ridge southbridge code | Marc Jones | 2017-06-26 | 1 | -0/+45 |
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index : coreboot.git | |
| Coreboot firmware sources | coreboot |
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