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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-10-17 08:34:31 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2022-02-05 07:59:04 +0000 |
| commit | 9ec7227c9b43df97e3422877b2539db21d47741b (patch) | |
| tree | 1caed1fb7bfd69ed47c505c199570cf124e26439 /src/soc/amd/stoneyridge | |
| parent | 7261b5ade5c2035da026837afdb20a7ec1252b19 (diff) | |
| download | coreboot-9ec7227c9b43df97e3422877b2539db21d47741b.tar.gz coreboot-9ec7227c9b43df97e3422877b2539db21d47741b.tar.bz2 coreboot-9ec7227c9b43df97e3422877b2539db21d47741b.zip | |
cpu/x86/lapic: Move LAPIC configuration to MP init
Implementation for setup_lapic() did two things -- call
enable_lapic() and virtual_wire_mode_init().
In PARALLEL_MP case enable_lapic() was redundant as it
was already executed prior to initialize_cpu() call.
For the !PARALLEL_MP case enable_lapic() is added to
AP CPUs.
Change-Id: I5caf94315776a499e9cf8f007251b61f51292dc5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/soc/amd/stoneyridge')
| -rw-r--r-- | src/soc/amd/stoneyridge/cpu.c | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c index 6be76bfde8d9..3cd3a9580ae1 100644 --- a/src/soc/amd/stoneyridge/cpu.c +++ b/src/soc/amd/stoneyridge/cpu.c @@ -9,7 +9,6 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> #include <cpu/x86/smm.h> -#include <cpu/x86/lapic.h> #include <device/device.h> #include <device/pci_ops.h> #include <soc/pci_devs.h> @@ -65,7 +64,6 @@ void mp_init_cpus(struct bus *cpu_bus) static void model_15_init(struct device *dev) { check_mca(); - setup_lapic(); /* * Per AMD, sync an undocumented MSR with the PSP base address. |