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| author | Subrata Banik <subratabanik@google.com> | 2022-01-28 23:49:31 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2022-02-02 07:39:51 +0000 |
| commit | 5a49f3aa7973cce8936bfe6600d2726904d24947 (patch) | |
| tree | 70b2ade378f5103ef4f57839a2d2bf8f362a82a9 /src/soc/intel/alderlake/Kconfig | |
| parent | 7ef471c67acfc4775efbd97590b931759c478380 (diff) | |
| download | coreboot-5a49f3aa7973cce8936bfe6600d2726904d24947.tar.gz coreboot-5a49f3aa7973cce8936bfe6600d2726904d24947.tar.bz2 coreboot-5a49f3aa7973cce8936bfe6600d2726904d24947.zip | |
soc/intel/alderlake: Use PMC IPC to disable HECI1
This patch allows common CSE block to disable HECI1 device using PMC
IPC command `0xA9`.
Select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC config for
Alder Lake to disable HECI1 device using PMC IPC.
Additionally, remove dead code that deals with HECI1 disabling using
in SMM as HECI1 disabling using PMC IPC is simpler solution.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I11a677173fd6fb38f7c09594a653aeea0df1332c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61458
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Diffstat (limited to 'src/soc/intel/alderlake/Kconfig')
| -rw-r--r-- | src/soc/intel/alderlake/Kconfig | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index fa950886841e..863150e7dc8d 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -78,6 +78,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 select SOC_INTEL_COMMON_BLOCK_SCS if SOC_INTEL_ALDERLAKE_PCH_N select SOC_INTEL_COMMON_BLOCK_HDA + select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC if DISABLE_HECI1_AT_PRE_BOOT select SOC_INTEL_COMMON_BLOCK_IPU select SOC_INTEL_COMMON_BLOCK_IRQ select SOC_INTEL_COMMON_BLOCK_MEMINIT |