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| author | Subrata Banik <subratabanik@google.com> | 2022-01-28 23:49:31 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2022-02-02 07:39:51 +0000 |
| commit | 5a49f3aa7973cce8936bfe6600d2726904d24947 (patch) | |
| tree | 70b2ade378f5103ef4f57839a2d2bf8f362a82a9 /src/soc | |
| parent | 7ef471c67acfc4775efbd97590b931759c478380 (diff) | |
| download | coreboot-5a49f3aa7973cce8936bfe6600d2726904d24947.tar.gz coreboot-5a49f3aa7973cce8936bfe6600d2726904d24947.tar.bz2 coreboot-5a49f3aa7973cce8936bfe6600d2726904d24947.zip | |
soc/intel/alderlake: Use PMC IPC to disable HECI1
This patch allows common CSE block to disable HECI1 device using PMC
IPC command `0xA9`.
Select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC config for
Alder Lake to disable HECI1 device using PMC IPC.
Additionally, remove dead code that deals with HECI1 disabling using
in SMM as HECI1 disabling using PMC IPC is simpler solution.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I11a677173fd6fb38f7c09594a653aeea0df1332c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61458
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Diffstat (limited to 'src/soc')
| -rw-r--r-- | src/soc/intel/alderlake/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/finalize.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/smihandler.c | 17 |
3 files changed, 3 insertions, 17 deletions
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index fa950886841e..863150e7dc8d 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -78,6 +78,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 select SOC_INTEL_COMMON_BLOCK_SCS if SOC_INTEL_ALDERLAKE_PCH_N select SOC_INTEL_COMMON_BLOCK_HDA + select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC if DISABLE_HECI1_AT_PRE_BOOT select SOC_INTEL_COMMON_BLOCK_IPU select SOC_INTEL_COMMON_BLOCK_IRQ select SOC_INTEL_COMMON_BLOCK_MEMINIT diff --git a/src/soc/intel/alderlake/finalize.c b/src/soc/intel/alderlake/finalize.c index 589ea5917a2c..880e1e02ed7c 100644 --- a/src/soc/intel/alderlake/finalize.c +++ b/src/soc/intel/alderlake/finalize.c @@ -106,6 +106,8 @@ static void soc_finalize(void *unused) tbt_finalize(); sa_finalize(); heci_finalize(); + if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) + heci1_disable(); /* Indicate finalize step with post code */ post_code(POST_OS_BOOT); diff --git a/src/soc/intel/alderlake/smihandler.c b/src/soc/intel/alderlake/smihandler.c index 61fecdf7bc01..e1fc5a03ad0d 100644 --- a/src/soc/intel/alderlake/smihandler.c +++ b/src/soc/intel/alderlake/smihandler.c @@ -1,28 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <device/pci_def.h> -#include <intelblocks/cse.h> #include <intelblocks/smihandler.h> #include <soc/soc_chip.h> #include <soc/pci_devs.h> #include <soc/pm.h> -/* - * Specific SOC SMI handler during ramstage finalize phase - * - * BIOS can't make CSME function disable as is due to POSTBOOT_SAI - * restriction in place from ADP chipset. Hence create SMI Handler to - * perform CSME function disabling logic during SMM mode. - */ -void smihandler_soc_at_finalize(void) -{ - if (!CONFIG(HECI_DISABLE_USING_SMM)) - return; - - if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) - heci1_disable(); -} - int smihandler_soc_disable_busmaster(pci_devfn_t dev) { /* Skip disabling PMC bus master to keep IO decode enabled */ |