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| author | Curtis Chen <curtis.chen@intel.com> | 2022-01-19 16:36:31 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-01-21 16:06:26 +0000 |
| commit | 38fcf40330adbbb3b93c29eb809a9a56504a63a5 (patch) | |
| tree | 11e15884f033d92bc0d79d5f3f92018ca0048452 /src/soc/intel/alderlake/chipset.cb | |
| parent | 77426ffa6c056d37b5a3b833051ae2f720bde597 (diff) | |
| download | coreboot-38fcf40330adbbb3b93c29eb809a9a56504a63a5.tar.gz coreboot-38fcf40330adbbb3b93c29eb809a9a56504a63a5.tar.bz2 coreboot-38fcf40330adbbb3b93c29eb809a9a56504a63a5.zip | |
soc/intel/alderlake: Add ADL-P 2+8+2 (28W) VR config
ADL-P 2+8+2 (28W) would have a match PD to ADL-P 4+8+2 (28W). Group them
into the same group core "ADL_P_282_482_28W_CORE".
BUG=b:211365920
TEST=Build and check fsp log to confirm the settings are set properly.
Signed-off-by: Curtis Chen <curtis.chen@intel.com>
Change-Id: I3f92c0f5d717dd33ac478fbaa883f3e972e7a7de
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel/alderlake/chipset.cb')
| -rw-r--r-- | src/soc/intel/alderlake/chipset.cb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/alderlake/chipset.cb b/src/soc/intel/alderlake/chipset.cb index e02cdadb7443..7de8f09ab1a6 100644 --- a/src/soc/intel/alderlake/chipset.cb +++ b/src/soc/intel/alderlake/chipset.cb @@ -8,7 +8,7 @@ chip soc/intel/alderlake .tdp_pl4 = 123, }" - register "power_limits_config[ADL_P_482_28W_CORE]" = "{ + register "power_limits_config[ADL_P_282_482_28W_CORE]" = "{ .tdp_pl1_override = 28, .tdp_pl2_override = 64, .tdp_pl4 = 90, |