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path: root/src/soc/intel/alderlake/chipset.cb
Commit message (Expand)AuthorAgeFilesLines
* soc/intel/alderlake: Disable hwp scalibility trackingBora Guvendik2023-07-131-0/+3
* soc/intel/alderlake: Disable SaGV reorderingBora Guvendik2023-07-131-0/+3
* soc/intel/alderlake: Reduce memory test sizeBora Guvendik2023-07-131-0/+3
* soc/intel/alderlake/{chipset.cb,chipset_pch_s.cb}: Set P2SB as hiddenMichał Żygowski2023-04-111-1/+1
* soc/intel/alderlake: Add ADL-P 4+4 with 28W TDPPatrick Rudolph2023-04-021-1/+1
* soc/intel/alderlake: add power limits for Alder Lake-N 7W socSimon Yang2022-09-081-0/+6
* soc/intel/alderlake: Add new pcie5 alias for raptorlakeBora Guvendik2022-08-311-0/+1
* soc/intel/alderlake: Rename pcie5 aliasBora Guvendik2022-08-291-1/+1
* soc/intel/alderlake: RPL-P power limits and VR settingsJeremy Compostella2022-07-041-0/+18
* soc/intel/alderlake: add power limits for Alder Lake-N SKUsVidya Gopalakrishnan2022-06-021-0/+18
* soc/intel/alderlake: Add support for UFS controllerMeera Ravindranath2022-04-131-0/+1
* soc/intel/adl: Replace dt `HeciEnabled` by `HECI1 disable` configSubrata Banik2022-01-251-1/+1
* soc/intel/alderlake: Add ADL-P 2+8+2 (28W) VR configCurtis Chen2022-01-211-1/+1
* soc/intel/alderlake: Add eMMC device into chipset.cbKrishna Prasad Bhat2022-01-181-0/+2
* soc/intel/alderlake: Update the ADL-P SKU parameters for VR domainsCurtis Chen2022-01-101-15/+9
* soc/intel/alderlake: Add ADLP 4+4+2 power configurationsCurtis Chen2021-11-251-1/+7
* soc/intel/alderlake: Set `pch_thermal_trip` for Dynamic Thermal ShutdownSubrata Banik2021-11-201-0/+5
* soc/intel/alderlake: add power limits for Alder Lake-M 282 SKUSumeet Pawnikar2021-10-011-1/+6
* soc/intel/alderlake: Add ADLP 242 power configurationsTracy Wu2021-09-291-0/+5
* soc/intel/alderlake: set power limits dynamically for thermalSumeet Pawnikar2021-09-031-5/+11
* soc/intel/adl: Update power limits for ADL-M SKUSumeet Pawnikar2021-08-201-0/+6
* soc/intel/alderlake: set default PL4 values for different SKUsSumeet Pawnikar2021-08-191-0/+4
* mb/*/{brya,adlrvp}: move cpu_cluster static configuration to chipset.cbMAULIK V VAGHELA2021-08-101-0/+2
* soc/intel/alderlake: Add support for I2C6 and I2C7Varshit B Pandya2021-07-201-0/+2
* soc/intel/alderlake: Correct Bus and Device of Touch Host ControllerVarshit B Pandya2021-07-051-2/+2
* soc/intel/adl: Add SKU specific power limits supportSumeet Pawnikar2021-06-071-0/+21
* soc/intel/alderlake: Add IDE-R and KT device into chipset.cbSubrata Banik2021-06-051-0/+2
* soc/intel/alderlake: Add CrashLog implementation for Intel ADLFrancois Toguo2021-05-061-1/+1
* soc/intel/alderlake: Remove obsolete CNVi Bluetooth PCI deviceCliff Huang2021-03-151-1/+0
* soc/intel/adl, mb/google/brya: Add IPU to devicetreeTim Wawrzynczak2021-03-051-0/+1
* soc/intel: hook up new gpio device in the soc chipsMichael Niewöhner2020-12-301-0/+1
* soc/intel/alderlake: Update chipset.cb for TCSS and USBEric Lai2020-12-291-6/+92
* soc/intel/alderlake: Align chipset.cb with pci_devs.hEric Lai2020-12-041-8/+9
* soc/intel/alderlake: Add initial chipset.cbTim Wawrzynczak2020-11-301-0/+67
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