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| author | Subrata Banik <subrata.banik@intel.com> | 2021-11-17 13:34:15 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2021-11-20 17:49:11 +0000 |
| commit | 8c45f236bc74a12819c4bc09a4b3e6d52bee3066 (patch) | |
| tree | a8385a98a508c1799de34fc3fac44debc57bf047 /src/soc/intel/alderlake/chipset.cb | |
| parent | 2ee30add352c56fbf5a49ed27705318adaff7893 (diff) | |
| download | coreboot-8c45f236bc74a12819c4bc09a4b3e6d52bee3066.tar.gz coreboot-8c45f236bc74a12819c4bc09a4b3e6d52bee3066.tar.bz2 coreboot-8c45f236bc74a12819c4bc09a4b3e6d52bee3066.zip | |
soc/intel/alderlake: Set `pch_thermal_trip` for Dynamic Thermal Shutdown
Set low maximum temp threshold value used for dynamic thermal sensor
shutdown consideration.
BUG=b:193774296
Change-Id: I7ee199c19a9d926a4135eeef3b3b481fbff74a79
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Diffstat (limited to 'src/soc/intel/alderlake/chipset.cb')
| -rw-r--r-- | src/soc/intel/alderlake/chipset.cb | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/chipset.cb b/src/soc/intel/alderlake/chipset.cb index 9a752dda189a..fc73a8982940 100644 --- a/src/soc/intel/alderlake/chipset.cb +++ b/src/soc/intel/alderlake/chipset.cb @@ -48,6 +48,11 @@ chip soc/intel/alderlake .tdp_pl4 = 123, }" + # NOTE: if any variant wants to override this value, use the same format + # as register "common_soc_config.pch_thermal_trip" = "value", instead of + # putting it under register "common_soc_config" in overridetree.cb file. + register "common_soc_config.pch_thermal_trip" = "100" + device domain 0 on device gpio 0 alias pch_gpio on end device pci 00.0 alias system_agent on end |