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| author | Sean Rhodes <sean@starlabs.systems> | 2022-01-19 08:13:38 +0000 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-15 16:18:20 +0000 |
| commit | 2d58d5c0529d47e6639b250d65c7d2f5c7152650 (patch) | |
| tree | e3fdfc8f3ddac215d64ad47362a796ac94b3bac4 /src/soc/intel/apollolake/chip.h | |
| parent | 7c2f57a4c7aee8ed63001d5db686917d17cf82f6 (diff) | |
| download | coreboot-2d58d5c0529d47e6639b250d65c7d2f5c7152650.tar.gz coreboot-2d58d5c0529d47e6639b250d65c7d2f5c7152650.tar.bz2 coreboot-2d58d5c0529d47e6639b250d65c7d2f5c7152650.zip | |
soc/apollolake: Make IO decode / enable register configurable
This allows the one 32bit register to be configured in the
devicetree in the same way that Skylake can be.
i.e. register "lpc_ioe".
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I598baca0f31b5350a4e6fdb7b7356fa6fb2d71ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel/apollolake/chip.h')
| -rw-r--r-- | src/soc/intel/apollolake/chip.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index f531381fac46..0073103e253b 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -106,6 +106,10 @@ struct soc_intel_apollolake_config { uint8_t gpe0_dw2; /* GPE0_95_64 STS/EN */ uint8_t gpe0_dw3; /* GPE0_127_96 STS/EN */ + /* LPC fixed enables and ranges */ + uint16_t lpc_iod; + uint16_t lpc_ioe; + /* Configure LPSS S0ix Enable */ uint8_t lpss_s0ix_enable; |