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| author | Martin Roth <martin.roth@se-eng.com> | 2014-12-07 14:57:26 -0700 |
|---|---|---|
| committer | Martin Roth <gaumless@gmail.com> | 2014-12-08 05:40:24 +0100 |
| commit | 99a3bba171695804624b8426052de0cd552f1455 (patch) | |
| tree | 14ddb97ccbabe30f448ac768729b865f191ee501 /src/soc/intel/baytrail/pcie.c | |
| parent | 7c96629e94a0e37d8bb565f19d3c20865da50bec (diff) | |
| download | coreboot-99a3bba171695804624b8426052de0cd552f1455.tar.gz coreboot-99a3bba171695804624b8426052de0cd552f1455.tar.bz2 coreboot-99a3bba171695804624b8426052de0cd552f1455.zip | |
intel/baytrail: Spelling fixes
Change-Id: Ideb58634a029d55746421ad1ea4b80811bca403c
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7705
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Diffstat (limited to 'src/soc/intel/baytrail/pcie.c')
| -rw-r--r-- | src/soc/intel/baytrail/pcie.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/baytrail/pcie.c b/src/soc/intel/baytrail/pcie.c index 4498f43a223d..71b90ded4764 100644 --- a/src/soc/intel/baytrail/pcie.c +++ b/src/soc/intel/baytrail/pcie.c @@ -80,7 +80,7 @@ static const struct reg_script init_static_after_exit_latency[] = { REG_PCI_RMW16(DSTS2, ~CTD, 0x6), /* Enable AER */ REG_PCI_OR16(DCTL_DSTS, URE | FEE | NFE | CEE), - /* Read and write back capabaility registers. */ + /* Read and write back capability registers. */ REG_PCI_OR32(0x34, 0), REG_PCI_OR32(0x80, 0), /* Retrain the link. */ |