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path: root/src/soc/intel/baytrail/pcie.c
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* src: Make PCI ID define names shorterFelix Singer2022-03-071-1/+1
* src: Use pci_dev_ops_pci where applicableAngel Pons2020-06-061-5/+1
* treewide: Remove "this file is part of" linesPatrick Georgi2020-05-111-1/+0
* soc/intel/baytrail: Use SPDX for GPL-2.0-only filesAngel Pons2020-04-061-13/+2
* soc: Remove copyright noticesPatrick Georgi2020-03-181-1/+0
* src: capitalize 'PCIe'Elyes HAOUAS2020-03-041-1/+1
* soc/intel: Rename some SMM support functionsKyösti Mälkki2019-08-151-1/+1
* soc/intel: Use config_of()Kyösti Mälkki2019-07-181-4/+4
* soc/intel/{baytrail,braswell}: Make use of generic set_subsystem()Kyösti Mälkki2019-03-221-11/+1
* device/pci: Fix PCI accessor headersKyösti Mälkki2019-03-011-0/+1
* src: Remove unneeded whitespaceElyes HAOUAS2018-10-231-1/+1
* soc/intel/baytrail: Get rid of device_tElyes HAOUAS2018-05-241-9/+10
* src/soc: Add required space before opening parenthesis '('Elyes HAOUAS2016-08-311-1/+1
* tree: drop last paragraph of GPL copyright headerPatrick Georgi2015-10-311-4/+0
* devicetree: Change scan_bus() prototype in device opsKyösti Mälkki2015-06-041-2/+2
* Remove address from GPLv2 headersPatrick Georgi2015-05-211-1/+1
* baytrail: fix the coding error on PCIe L1 exit latencyKevin L Lee2015-04-101-1/+1
* Baytrail: Prior to PCI scan, wait for LCTL to be active in 50 msKevin Hsieh2015-04-101-1/+14
* baytrail: Change all SoC headers to <soc/headername.h> systemJulius Werner2015-04-071-4/+4
* Baytrail: Fix no_dev_behind_port not executed for RP1/2/3.Kenji Chen2015-04-041-0/+1
* Baytrail: Change PCIe root disable algorithmKenji Chen2015-04-021-2/+37
* intel/baytrail: Spelling fixesMartin Roth2014-12-081-1/+1
* baytrail/rambi: S3 support and other updatesKein Yuan2014-10-221-0/+6
* baytrail: utilize reg_script_run_on_dev()Aaron Durbin2014-05-101-9/+2
* baytrail: pcie: Root port initializationAaron Durbin2014-05-071-0/+230