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| author | Angel Pons <th3fanbus@gmail.com> | 2021-04-19 17:12:42 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2021-06-14 09:59:25 +0000 |
| commit | 07baa7a7f06369d9dc795c5a9b34314e88d14dd8 (patch) | |
| tree | 7e226de800d75fc2fbe32af3144720c743b0e5f8 /src/soc/intel/broadwell/pch/lpc.c | |
| parent | e42ce6bb499031cbe4cdbad19314d2c9971b2186 (diff) | |
| download | coreboot-07baa7a7f06369d9dc795c5a9b34314e88d14dd8.tar.gz coreboot-07baa7a7f06369d9dc795c5a9b34314e88d14dd8.tar.bz2 coreboot-07baa7a7f06369d9dc795c5a9b34314e88d14dd8.zip | |
soc/intel/broadwell: Re-do SerialIO UART console support
Use the same code from Lynx Point on Broadwell, and adjust as needed.
Also add a config file to ensure the code gets build-tested.
Tested on out-of-tree Compal LA-A992P (Haswell ULT), UART 0 works.
Change-Id: I527024098738700d5fbaf3e27cf4db331a0322bd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/soc/intel/broadwell/pch/lpc.c')
| -rw-r--r-- | src/soc/intel/broadwell/pch/lpc.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/soc/intel/broadwell/pch/lpc.c b/src/soc/intel/broadwell/pch/lpc.c index e32ae361762d..4b4aa9f36cf3 100644 --- a/src/soc/intel/broadwell/pch/lpc.c +++ b/src/soc/intel/broadwell/pch/lpc.c @@ -604,11 +604,12 @@ static unsigned long broadwell_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp) { - if (CONFIG(INTEL_PCH_UART_CONSOLE)) + if (CONFIG(SERIALIO_UART_CONSOLE)) { current = acpi_write_dbg2_pci_uart(rsdp, current, - (CONFIG_INTEL_PCH_UART_CONSOLE_NUMBER == 1) ? + (CONFIG_UART_FOR_CONSOLE == 1) ? PCH_DEV_UART1 : PCH_DEV_UART0, - ACPI_ACCESS_SIZE_BYTE_ACCESS); + ACPI_ACCESS_SIZE_DWORD_ACCESS); + } return acpi_write_hpet(device, current, rsdp); } |