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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-07-12 13:10:19 +0300 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2019-07-21 18:58:01 +0000 |
| commit | 71756c21afd14f4114c597487406eb53e23730b2 (patch) | |
| tree | 7ccb61cf5eb3a5b3fb3024327fce58d141c4e928 /src/soc/intel/broadwell/systemagent.c | |
| parent | 6046eb405a4f1cbb4df1ed0d23276f333bc0998b (diff) | |
| download | coreboot-71756c21afd14f4114c597487406eb53e23730b2.tar.gz coreboot-71756c21afd14f4114c597487406eb53e23730b2.tar.bz2 coreboot-71756c21afd14f4114c597487406eb53e23730b2.zip | |
soc/intel: Expand SA_DEV_ROOT for ramstage
We do not want to disguise somewhat complex function
calls as simple macros.
Change-Id: I298f7f9a1c6a64cfba454e919eeaedc7bb2d4801
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/broadwell/systemagent.c')
| -rw-r--r-- | src/soc/intel/broadwell/systemagent.c | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/src/soc/intel/broadwell/systemagent.c b/src/soc/intel/broadwell/systemagent.c index c6444b15e8f5..b6b5608a2407 100644 --- a/src/soc/intel/broadwell/systemagent.c +++ b/src/soc/intel/broadwell/systemagent.c @@ -32,19 +32,22 @@ u8 systemagent_revision(void) { - return pci_read_config8(SA_DEV_ROOT, PCI_REVISION_ID); + struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); + return pci_read_config8(sa_dev, PCI_REVISION_ID); } uintptr_t sa_get_tolud_base(void) { + struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); /* Bit 0 is lock bit, not part of address */ - return pci_read_config32(SA_DEV_ROOT, TOLUD) & ~1; + return pci_read_config32(sa_dev, TOLUD) & ~1; } uintptr_t sa_get_gsm_base(void) { + struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); /* Bit 0 is lock bit, not part of address */ - return pci_read_config32(SA_DEV_ROOT, BGSM) & ~1; + return pci_read_config32(sa_dev, BGSM) & ~1; } static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base, @@ -291,6 +294,7 @@ static void mc_add_dram_resources(struct device *dev, int *resource_cnt) uint64_t mc_values[NUM_MAP_ENTRIES]; unsigned long dpr_size = 0; u32 dpr_reg; + struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); /* Read in the MAP registers and report their values. */ mc_read_map_entries(dev, &mc_values[0]); @@ -302,7 +306,7 @@ static void mc_add_dram_resources(struct device *dev, int *resource_cnt) * the DPR register reports the TOP of the region, which is the same * as TSEG base. The region size is reported in MiB in bits 11:4. */ - dpr_reg = pci_read_config32(SA_DEV_ROOT, DPR); + dpr_reg = pci_read_config32(sa_dev, DPR); if (dpr_reg & DPR_EPM) { dpr_size = (dpr_reg & DPR_SIZE_MASK) << 16; printk(BIOS_INFO, "DPR SIZE: 0x%lx\n", dpr_size); |