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| author | Lijian Zhao <lijian.zhao@intel.com> | 2018-02-15 17:11:00 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-02-22 09:58:39 +0000 |
| commit | 9672b540874bf3a27df0b35ae94ada32e5a8c601 (patch) | |
| tree | 688015ba85ad7e4306cad2a97d12daff3894c0ad /src/soc/intel/cannonlake/acpi/southbridge.asl | |
| parent | 206821ee2f4ecae68fb292d0075bb82acac0c8bb (diff) | |
| download | coreboot-9672b540874bf3a27df0b35ae94ada32e5a8c601.tar.gz coreboot-9672b540874bf3a27df0b35ae94ada32e5a8c601.tar.bz2 coreboot-9672b540874bf3a27df0b35ae94ada32e5a8c601.zip | |
soc/intel/cannonlake: Add emmc/sdc port id
EMMC and SD Controller port id listed here, the port id definition came
from Cannonlake BIOS Writer Guide 570374.
BUG=None
TEST=None
Change-Id: I901e90c47b08bb013fcfee5def610e320a7ac19a
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23789
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Diffstat (limited to 'src/soc/intel/cannonlake/acpi/southbridge.asl')
0 files changed, 0 insertions, 0 deletions