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| author | Meera Ravindranath <meera.ravindranath@intel.com> | 2020-02-12 16:01:22 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-02-25 10:13:36 +0000 |
| commit | 3f4af0da938e0d9f4d80e77a3d8abd1f6400e57e (patch) | |
| tree | f91f342cd93dbcf175016681b3fbdf887688886d /src/soc/intel/common/block/include/intelblocks/mp_init.h | |
| parent | 7e8998466f6b0cfa410af94da41b18859d6379f2 (diff) | |
| download | coreboot-3f4af0da938e0d9f4d80e77a3d8abd1f6400e57e.tar.gz coreboot-3f4af0da938e0d9f4d80e77a3d8abd1f6400e57e.tar.bz2 coreboot-3f4af0da938e0d9f4d80e77a3d8abd1f6400e57e.zip | |
soc/intel/common: Update Jasper Lake Device IDs
Update Jasper Lake CPU, SA and PCH IDs.
BUG=b:149185282
BRANCH=None
TEST=Compilation for Jasper Lake board is working
Change-Id: I2c9ec1eb4236184b981d99250f263172c82f7117
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Signed-off-by: Varshit Pandya <varshit.b.pandya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Diffstat (limited to 'src/soc/intel/common/block/include/intelblocks/mp_init.h')
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/mp_init.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/mp_init.h b/src/soc/intel/common/block/include/intelblocks/mp_init.h index c0c58afc8d50..4c528e0f7873 100644 --- a/src/soc/intel/common/block/include/intelblocks/mp_init.h +++ b/src/soc/intel/common/block/include/intelblocks/mp_init.h @@ -46,6 +46,7 @@ #define CPUID_COFFEELAKE_R0 0x906ed #define CPUID_ICELAKE_A0 0x706e0 #define CPUID_ICELAKE_B0 0x706e1 +#define CPUID_JASPERLAKE_A0 0x906c0 #define CPUID_COMETLAKE_U_A0 0xa0660 #define CPUID_COMETLAKE_U_K0_S0 0xa0661 #define CPUID_COMETLAKE_H_S_6_2_G0 0xa0650 |