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| author | Gaggery Tsai <gaggery.tsai@intel.com> | 2019-11-04 20:49:10 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-12-02 12:04:38 +0000 |
| commit | fdcc9ab317af2ae9cd69cb2490d3a4444180429a (patch) | |
| tree | e8ffba4d330aa12dd1dab94408e15bc871fcc76b /src/soc/intel/common/block/include/intelblocks/mp_init.h | |
| parent | c9b13594eb8d425e54a126b5c10e3f6fbc41528b (diff) | |
| download | coreboot-fdcc9ab317af2ae9cd69cb2490d3a4444180429a.tar.gz coreboot-fdcc9ab317af2ae9cd69cb2490d3a4444180429a.tar.bz2 coreboot-fdcc9ab317af2ae9cd69cb2490d3a4444180429a.zip | |
src/soc/intel: Add Cometlake-S and CMP-H skus
This patch adds some sku support for CML-S CPU and CMP-H chips.
According to doc #605546:
CML-S (6+2) G0: A0650h
CML-S (6+2) G1: A0653h
CML-S (10+2, 8+2) P0: A0651h
CML-S (6+2, 10+2) Q0/P1: A0654h
CMP-H HM470: 068Dh
CMP-H WM490: 068Eh
CMP-H QM480: 068Ch
CMP-H H470: 0684h
CMP-H Z490: 0685h
CMP-H Q470: 0687h
TEST=Boot with CML-S (6+2) G1 + CMP-H WM490 and IDs are recognized
Change-Id: I6bda09070ec330033eff95329448ace57e87144f
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36684
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel/common/block/include/intelblocks/mp_init.h')
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/mp_init.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/soc/intel/common/block/include/intelblocks/mp_init.h b/src/soc/intel/common/block/include/intelblocks/mp_init.h index e5475383f702..aaf1793a146a 100644 --- a/src/soc/intel/common/block/include/intelblocks/mp_init.h +++ b/src/soc/intel/common/block/include/intelblocks/mp_init.h @@ -49,8 +49,10 @@ #define CPUID_ICELAKE_B0 0x706e1 #define CPUID_COMETLAKE_U_A0 0xa0660 #define CPUID_COMETLAKE_U_K0_S0 0xa0661 -#define CPUID_COMETLAKE_H_S_6_2_P0 0xa0650 +#define CPUID_COMETLAKE_H_S_6_2_G0 0xa0650 +#define CPUID_COMETLAKE_H_S_6_2_G1 0xa0653 #define CPUID_COMETLAKE_H_S_10_2_P0 0xa0651 +#define CPUID_COMETLAKE_H_S_10_2_Q0_P1 0xa0654 #define CPUID_TIGERLAKE_A0 0x806c0 /* |