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| author | Angel Pons <th3fanbus@gmail.com> | 2021-02-19 20:08:50 +0100 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2021-03-01 19:39:27 +0000 |
| commit | e178df27dd8e30c34fda568c7fa890512a55e7f0 (patch) | |
| tree | 70031f8ebfb56271655afa6d05a25cbbdb694dbf /src/soc/intel/common/pch | |
| parent | 19af7bc822ada5a60ffbbd5fe233434cbbf9ae09 (diff) | |
| download | coreboot-e178df27dd8e30c34fda568c7fa890512a55e7f0.tar.gz coreboot-e178df27dd8e30c34fda568c7fa890512a55e7f0.tar.bz2 coreboot-e178df27dd8e30c34fda568c7fa890512a55e7f0.zip | |
soc/intel: Factor out common smbus.h
Change-Id: I31bb406bd2cf371ee935aa31777307043b2ee61a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50942
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/common/pch')
| -rw-r--r-- | src/soc/intel/common/pch/include/intelpch/smbus.h | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/src/soc/intel/common/pch/include/intelpch/smbus.h b/src/soc/intel/common/pch/include/intelpch/smbus.h new file mode 100644 index 000000000000..238da2b73b33 --- /dev/null +++ b/src/soc/intel/common/pch/include/intelpch/smbus.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _INTELPCH_SMBUS_H_ +#define _INTELPCH_SMBUS_H_ + +/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */ +#define TCO1_STS 0x04 +#define TCO_TIMEOUT (1 << 3) +#define TCO2_STS 0x06 +#define TCO_STS_SECOND_TO (1 << 1) +#define TCO_INTRD_DET (1 << 0) +#define TCO1_CNT 0x08 +#define TCO_LOCK (1 << 12) +#define TCO_TMR_HLT (1 << 11) +#define TCO2_CNT 0x0A +#define TCO_INTRD_SEL_MASK (3 << 1) +#define TCO_INTRD_SEL_SMI (1 << 2) +#define TCO_INTRD_SEL_INT (1 << 1) + +/* + * Default slave address value for PCH. This value is set to match default + * value set by hardware. It is useful since PCH is able to respond even + * before CPU is up. This is reset by RSMRST# but not by PLTRST#. + */ +#define SMBUS_SLAVE_ADDR 0x44 + +#endif |