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| author | Felix Held <felix-coreboot@felixheld.de> | 2021-07-13 00:54:32 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-07-14 02:24:39 +0000 |
| commit | 1b46e76df9ef0a4b38d782732ee914ab70667bfa (patch) | |
| tree | 83b3471f79037cc7376e2817ddd2905922d4f7eb /src/soc/intel/common | |
| parent | e3f7ef22864402e72e1fa6c1df3bc79199c40bdc (diff) | |
| download | coreboot-1b46e76df9ef0a4b38d782732ee914ab70667bfa.tar.gz coreboot-1b46e76df9ef0a4b38d782732ee914ab70667bfa.tar.bz2 coreboot-1b46e76df9ef0a4b38d782732ee914ab70667bfa.zip | |
include/cpu/x86/msr: introduce IA32_MC_*(x) macros
When accessing the MCA MSRs, the MCA bank number gets multiplied by 4
and added to the IA32_MC0_* define to get the MSR number. Add a macro
that already does this calculation to avoid open coding this repeatedly.
Change-Id: I2de753b8c8ac8dcff5a94d5bba43aa13bbf94b99
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56243
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/common')
| -rw-r--r-- | src/soc/intel/common/block/cpu/cpulib.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c index 81e42aeda5b4..9e95b0f9f4fe 100644 --- a/src/soc/intel/common/block/cpu/cpulib.c +++ b/src/soc/intel/common/block/cpu/cpulib.c @@ -348,9 +348,9 @@ void mca_configure(void) for (i = 0; i < num_banks; i++) { /* Clear the machine check status */ - wrmsr(IA32_MC0_STATUS + (i * 4), msr); + wrmsr(IA32_MC_STATUS(i), msr); /* Initialize machine checks */ - wrmsr(IA32_MC0_CTL + i * 4, + wrmsr(IA32_MC_CTL(i), (msr_t) {.lo = 0xffffffff, .hi = 0xffffffff}); } } |