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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2020-02-24 13:43:39 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-04 15:43:30 +0000 |
| commit | 79ccc6933284ca02d17d9e1eda9a531ce43e1f65 (patch) | |
| tree | 49fe1b78916338575b1a6bec931e2fb885cc311a /src/soc/intel/icelake/chip.h | |
| parent | f3161df2eba8d61445372a9c732c61a1947064bd (diff) | |
| download | coreboot-79ccc6933284ca02d17d9e1eda9a531ce43e1f65.tar.gz coreboot-79ccc6933284ca02d17d9e1eda9a531ce43e1f65.tar.bz2 coreboot-79ccc6933284ca02d17d9e1eda9a531ce43e1f65.zip | |
src: capitalize 'PCIe'
Change-Id: I55bbb535372dc9af556b95ba162f02ffead2b9e2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39101
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/intel/icelake/chip.h')
| -rw-r--r-- | src/soc/intel/icelake/chip.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/icelake/chip.h b/src/soc/intel/icelake/chip.h index 569160f41f0b..56f89db5e714 100644 --- a/src/soc/intel/icelake/chip.h +++ b/src/soc/intel/icelake/chip.h @@ -134,7 +134,7 @@ struct soc_intel_icelake_config { /* PCIe Root Ports */ uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS]; - /* PCIe output clocks type to Pcie devices. + /* PCIe output clocks type to PCIe devices. * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use, * 0xFF: not used */ uint8_t PcieClkSrcUsage[CONFIG_MAX_ROOT_PORTS]; |