diff options
| author | Michael Niewöhner <foss@mniewoehner.de> | 2020-11-23 22:02:20 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-09-23 06:31:48 +0000 |
| commit | 85610d8d86de10cdb8c82b61290501ee0b3cf742 (patch) | |
| tree | 06e8e073dd06f153443a461d1dc5c61bc1d202bd /src/soc/intel/icelake | |
| parent | 74da5f1e7451c80b8a8420dc79d825074c6ca823 (diff) | |
| download | coreboot-85610d8d86de10cdb8c82b61290501ee0b3cf742.tar.gz coreboot-85610d8d86de10cdb8c82b61290501ee0b3cf742.tar.bz2 coreboot-85610d8d86de10cdb8c82b61290501ee0b3cf742.zip | |
soc/intel/{xeon-sp,icl,tgl,jsl,ehl}: add NMI_{EN,STS} registers
Add NMI_EN and NMI_STS registers, so NMI interrupts can be used.
References:
- XEON-SP: Intel doc# 633935-005 and 547817 rev1.5
- ICL-LP: Intel doc# 341081-002
- TGL-LP: Intel doc# 631120-001
- TGL-H: Intel doc# 636174-002
- JSL: Intel doc# 634545-001
- EHL: Intel doc# 636722-002
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I2621f4495dfd4f95f9774d9081e44c604de830a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48102
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Lance Zhao
Diffstat (limited to 'src/soc/intel/icelake')
| -rw-r--r-- | src/soc/intel/icelake/gpio.c | 10 | ||||
| -rw-r--r-- | src/soc/intel/icelake/include/soc/gpio_defs.h | 2 |
2 files changed, 12 insertions, 0 deletions
diff --git a/src/soc/intel/icelake/gpio.c b/src/soc/intel/icelake/gpio.c index 3ee17e675434..7febd01b53f9 100644 --- a/src/soc/intel/icelake/gpio.c +++ b/src/soc/intel/icelake/gpio.c @@ -74,6 +74,8 @@ static const struct pad_community icl_communities[TOTAL_GPIO_COMM] = { .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0, + .gpi_nmi_en_reg_0 = GPI_NMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPP_GBA", .acpi_path = "\\_SB.PCI0.GPIO", @@ -94,6 +96,8 @@ static const struct pad_community icl_communities[TOTAL_GPIO_COMM] = { .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0, + .gpi_nmi_en_reg_0 = GPI_NMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPP_HDF", .acpi_path = "\\_SB.PCI0.GPIO", @@ -114,6 +118,8 @@ static const struct pad_community icl_communities[TOTAL_GPIO_COMM] = { .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0, + .gpi_nmi_en_reg_0 = GPI_NMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPD", .acpi_path = "\\_SB.PCI0.GPIO", @@ -134,6 +140,8 @@ static const struct pad_community icl_communities[TOTAL_GPIO_COMM] = { .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0, + .gpi_nmi_en_reg_0 = GPI_NMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPP_CE", .acpi_path = "\\_SB.PCI0.GPIO", @@ -154,6 +162,8 @@ static const struct pad_community icl_communities[TOTAL_GPIO_COMM] = { .gpi_int_en_reg_0 = GPI_INT_EN_0, .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .gpi_nmi_sts_reg_0 = GPI_NMI_STS_0, + .gpi_nmi_en_reg_0 = GPI_NMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, .name = "GPP_RS", .acpi_path = "\\_SB.PCI0.GPIO", diff --git a/src/soc/intel/icelake/include/soc/gpio_defs.h b/src/soc/intel/icelake/include/soc/gpio_defs.h index 577ca5f42701..b9238a5d2b64 100644 --- a/src/soc/intel/icelake/include/soc/gpio_defs.h +++ b/src/soc/intel/icelake/include/soc/gpio_defs.h @@ -255,6 +255,8 @@ #define GPI_INT_EN_0 0x110 #define GPI_SMI_STS_0 0x180 #define GPI_SMI_EN_0 0x1A0 +#define GPI_NMI_STS_0 0x1b0 +#define GPI_NMI_EN_0 0x1d0 #define PAD_CFG_BASE 0x600 #endif |