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| author | Lean Sheng Tan <lean.sheng.tan@intel.com> | 2021-06-15 22:05:42 -0700 |
|---|---|---|
| committer | Werner Zeh <werner.zeh@siemens.com> | 2021-06-18 06:03:25 +0000 |
| commit | 8bbff1f55494db50b92306a5f65c634c87e9c9d7 (patch) | |
| tree | 514400fc04336a74377061f8ada672ac645ea35f /src/soc/intel/jasperlake/fsp_params.c | |
| parent | fefc2ea4c41a1a786fb0b0dc890da1d1370f0731 (diff) | |
| download | coreboot-8bbff1f55494db50b92306a5f65c634c87e9c9d7.tar.gz coreboot-8bbff1f55494db50b92306a5f65c634c87e9c9d7.tar.bz2 coreboot-8bbff1f55494db50b92306a5f65c634c87e9c9d7.zip | |
soc/intel/elkhartlake: Make use of FSP_ARRAY_LOAD macro
Use FSP_ARRAY_LOAD macro for checking and loading array type
configs into array type UPDs to increase readability.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I2562977e55f8909038697f7e19b82ec6b5e47fae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/soc/intel/jasperlake/fsp_params.c')
0 files changed, 0 insertions, 0 deletions