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| author | Lee Leahy <leroy.p.leahy@intel.com> | 2016-07-25 07:41:54 -0700 |
|---|---|---|
| committer | Lee Leahy <leroy.p.leahy@intel.com> | 2016-08-05 01:50:45 +0200 |
| commit | 102f6253600cfa3f741c0d1d126436d612daa203 (patch) | |
| tree | dc3d0c6376b405dc053e4f4c9c864d30cf4737eb /src/soc/intel/quark/Makefile.inc | |
| parent | 6e05c33626e128c383470579f423b1ee569302ba (diff) | |
| download | coreboot-102f6253600cfa3f741c0d1d126436d612daa203.tar.gz coreboot-102f6253600cfa3f741c0d1d126436d612daa203.tar.bz2 coreboot-102f6253600cfa3f741c0d1d126436d612daa203.zip | |
soc/intel/quark: Add FSP 2.0 boot block support
Add the pieces necessary to successfully build and run bootblock using
the FSP 2.0 build.
TEST=Build and run bootblock on Galileo Gen2
Change-Id: I2377f0b0147196f100396b8cd7eaca8f92d6932f
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15865
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel/quark/Makefile.inc')
| -rw-r--r-- | src/soc/intel/quark/Makefile.inc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc index 4740ec77a748..a6454d9a1c18 100644 --- a/src/soc/intel/quark/Makefile.inc +++ b/src/soc/intel/quark/Makefile.inc @@ -35,18 +35,21 @@ ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-y += chip.c ramstage-y += ehci.c ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += fsp1_1.c +ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += fsp2_0.c ramstage-y += gpio_i2c.c ramstage-y += i2c.c ramstage-y += lpc.c ramstage-y += memmap.c ramstage-y += northcluster.c ramstage-y += reg_access.c +ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c ramstage-y += tsc_freq.c ramstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c ramstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c CPPFLAGS_common += -I$(src)/soc/intel/quark CPPFLAGS_common += -I$(src)/soc/intel/quark/include +CPPFLAGS_common += -I$(src)/soc/intel/quark/include/soc/fsp # Chipset microcode path CPPFLAGS_common += -I3rdparty/blobs/soc/intel/quark |