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| author | Lee Leahy <leroy.p.leahy@intel.com> | 2016-02-07 10:42:14 -0800 |
|---|---|---|
| committer | Leroy P Leahy <leroy.p.leahy@intel.com> | 2016-02-08 20:36:15 +0100 |
| commit | a7ba56e3ce56c8569e2ac5ddb2d2b6c71458d9cb (patch) | |
| tree | bb23130f7a12e5d566f11be031c492b90c258de9 /src/soc/intel/quark/Makefile.inc | |
| parent | 9fd0895cb4a8cf8d4ece09d62628b6d4b91177ae (diff) | |
| download | coreboot-a7ba56e3ce56c8569e2ac5ddb2d2b6c71458d9cb.tar.gz coreboot-a7ba56e3ce56c8569e2ac5ddb2d2b6c71458d9cb.tar.bz2 coreboot-a7ba56e3ce56c8569e2ac5ddb2d2b6c71458d9cb.zip | |
soc/intel/quark: Add TempRamInit support
Successfully invoke TempRamInit from the FSP binary:
* Don't relocate the FSP binary image
* Copy the FSP binary into ESRAM
* Specify Kconfig values to easily debug ESRAM and TempRamInit code
* Specify the FSP binary file location
* Specify the FSP binary image ID
* Specify where in the flash image the FSP image must reside
* Specify the FSP data file location
* Specify where to place the FSP data file in the flash image
* Specify where in the ESRAM the FSP image must reside
Test 1 on Galileo:
* Edit the src/mainboard/intel/galileo/Makefile.inc file
* Add "select ADD_FSP_PDAT_FILE"
* Add "select ADD_FSP_RAW_BIN"
* Add "select ADD_RMU_FILE"
* Add "select ENABLE_DEBUG_LED_FINDFSP"
* Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Testing is successful if the SD LED is on indicating that the FSP.bin
file was properly located, The test fails if the SD LED is flashing.
Test 2 on Galileo:
* Edit the src/mainboard/intel/galileo/Makefile.inc file
* Remove "select ENABLE_DEBUG_LED_FINDFSP"
* Add "select ENABLE_DEBUG_LED_TEMPRAMINIT"
* Testing is successful if the SD LED is on indicating that the FSP.bin
file was properly located, The test fails if the SD LED is flashing.
Change-Id: I1e2e413a8573f750c611b0f9df101b2c869a789e
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13443
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/intel/quark/Makefile.inc')
| -rw-r--r-- | src/soc/intel/quark/Makefile.inc | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc index 8e24d9b44f96..880f1d484cb0 100644 --- a/src/soc/intel/quark/Makefile.inc +++ b/src/soc/intel/quark/Makefile.inc @@ -27,6 +27,18 @@ CPPFLAGS_common += -I$(src)/soc/intel/quark/include # Chipset microcode path CPPFLAGS_common += -I3rdparty/blobs/soc/intel/quark +# Add the FSP binary to the CBFS image +cbfs-files-$(CONFIG_ADD_FSP_RAW_BIN) += fsp.bin +fsp.bin-file := $(call strip_quotes,$(CONFIG_FSP_FILE)) +fsp.bin-position := $(CONFIG_FSP_LOC) +fsp.bin-type := raw + +# Add the platform data file to the CBFS image +cbfs-files-$(CONFIG_ADD_FSP_PDAT_FILE) += pdat.bin +pdat.bin-file := $(call strip_quotes,$(CONFIG_FSP_PDAT_FILE)) +pdat.bin-position := $(CONFIG_FSP_PDAT_LOC) +pdat.bin-type := raw + # Add the chipset microcode file to the CBFS image cbfs-files-$(CONFIG_ADD_RMU_FILE) += rmu.bin rmu.bin-file := $(call strip_quotes,$(CONFIG_RMU_FILE)) |