diff options
| author | Karthikeyan Ramasubramanian <kramasub@chromium.org> | 2019-04-23 15:18:51 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-04-29 12:18:27 +0000 |
| commit | c126084bc53e0f74f6085f4f84b5bc387d701a4f (patch) | |
| tree | 2bd881e538ec2fb83a1b63982ae1fdbd28956401 /src/soc/intel/skylake/include/soc/gpio_defs.h | |
| parent | 91ead42f4bcfcc41190876343ab1cae2c35fb846 (diff) | |
| download | coreboot-c126084bc53e0f74f6085f4f84b5bc387d701a4f.tar.gz coreboot-c126084bc53e0f74f6085f4f84b5bc387d701a4f.tar.bz2 coreboot-c126084bc53e0f74f6085f4f84b5bc387d701a4f.zip | |
soc/intel: Add GPI interrupt config register offset info
Add the offset information for GPI interrupt status and enable register
in the pad_community structure. Populate the concerned information for
individual SoCs. This offset information is required to clear the
interrupt configuration during the bootup.
BUG=b:130593883
BRANCH=None
TEST=Ensure that the interrupt configuration are cleared during bootup.
Ensured that the system boots to ChromeOS.
Change-Id: I8af877a734e8d49b700d720b736da8764985a8f8
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/skylake/include/soc/gpio_defs.h')
| -rw-r--r-- | src/soc/intel/skylake/include/soc/gpio_defs.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/include/soc/gpio_defs.h b/src/soc/intel/skylake/include/soc/gpio_defs.h index 1c143a2c43c5..321d3c20c34c 100644 --- a/src/soc/intel/skylake/include/soc/gpio_defs.h +++ b/src/soc/intel/skylake/include/soc/gpio_defs.h @@ -225,6 +225,8 @@ #define GPIO_DRIVER_IRQ_ROUTE_IRQ15 8 #define HOSTSW_OWN_REG_0 0xd0 #define PAD_CFG_BASE 0x400 +#define GPI_INT_STS_0 0x100 +#define GPI_INT_EN_0 0x120 #define GPI_SMI_STS_0 0x180 #define GPI_SMI_EN_0 0x1a0 |