coreboot.git - Coreboot firmware sources

	Commit message (Expand)	Author	Age	Files	Lines
*	soc/intel: Remove unused <stddef.h>	Elyes Haouas	2023-01-20	1	-3/+1
*	soc/intel/{skl,cnl}: add NMI_{EN,STS} registers	Michael Niewöhner	2020-12-04	1	-0/+2
*	treewide: Remove "this file is part of" lines	Patrick Georgi	2020-05-11	1	-1/+0
*	soc/intel/skylake: Use SPDX for GPL-2.0-only files	Angel Pons	2020-04-06	1	-13/+2
*	soc: Remove copyright notices	Patrick Georgi	2020-03-18	1	-1/+0
*	soc/intel: Add GPI interrupt config register offset info	Karthikeyan Ramasubramanian	2019-04-29	1	-0/+2
*	coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)	Julius Werner	2019-03-08	1	-1/+1
*	soc/intel/skylake: Use common/block/gpio	Hannah Williams	2017-10-02	1	-117/+28
*	soc/intel/skylake: Add SKL SOC PCH H GPIO support	Li Cheng Sooi	2017-03-09	1	-194/+5
*	soc/intel/skylake: Remove pad configuration size hardcoding	Subrata Banik	2016-11-30	1	-0/+1
*	soc/intel/skylake: Cleanup patch for Skylake SoC	Barnali Sarkar	2016-08-08	1	-1/+0
*	skylake: gpio: Add support for setting 1.8V tolerant	Duncan Laurie	2016-06-09	1	-0/+5
*	tree: drop last paragraph of GPL copyright header	Patrick Georgi	2015-10-31	1	-4/+0
*	intel/skylake: gpio macro adding - gpio output with term and 20k pd	robbie zhang	2015-08-29	1	-0/+1
*	skylake: provide GPE0 routing devicetree configuration	Aaron Durbin	2015-08-14	1	-4/+27
*	Skylake: Add ASL code to enable GPIO controller	Archana Patni	2015-08-14	1	-0/+5
*	skylake: provide native gpio functionality	Aaron Durbin	2015-08-14	1	-0/+479