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| author | jzhao80 <john.zhao@intel.com> | 2022-01-10 07:54:57 -0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-01-12 16:09:47 +0000 |
| commit | 6c4edff487d365d40fbd6fb0eb3332492a947ada (patch) | |
| tree | 6febc7ba6aa1a6878343a83f5e270b0dd5d9a771 /src/soc/intel/tigerlake/Makefile.inc | |
| parent | a421b1a289fd173da609a4d1e2625c44ad1faad4 (diff) | |
| download | coreboot-6c4edff487d365d40fbd6fb0eb3332492a947ada.tar.gz coreboot-6c4edff487d365d40fbd6fb0eb3332492a947ada.tar.bz2 coreboot-6c4edff487d365d40fbd6fb0eb3332492a947ada.zip | |
soc/intel/tigerlake: Implement function to map physical port to EC port
Currently coreboot and EC had different logic to interpret TCSS port
number which would break retimer update functionality since coreboot
would pass wrong port information to EC.
This change clones the implementation on Alder Lake which converts
the phyiscal port mapping to EC's abstract port mapping.
BUG=b:207057940
BRANCH=None
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: If4451598dbb83528ae6d88dbc1b65c206f24fe1f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60972
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel/tigerlake/Makefile.inc')
| -rw-r--r-- | src/soc/intel/tigerlake/Makefile.inc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/Makefile.inc b/src/soc/intel/tigerlake/Makefile.inc index 25a1d6541002..0b616bee3ce3 100644 --- a/src/soc/intel/tigerlake/Makefile.inc +++ b/src/soc/intel/tigerlake/Makefile.inc @@ -37,6 +37,7 @@ ramstage-y += p2sb.c ramstage-y += pcie_rp.c ramstage-y += pmc.c ramstage-y += reset.c +ramstage-y += retimer.c ramstage-y += soundwire.c ramstage-y += systemagent.c ramstage-y += xhci.c |