diff options
| author | Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> | 2020-07-20 15:44:59 +0530 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2020-07-25 00:07:36 +0000 |
| commit | 1a621507098a16de167f2904aa2f9f23e9bff800 (patch) | |
| tree | 3df2560e747babc3b6df5d15f98a449066f19888 /src/soc/intel/tigerlake/chip.h | |
| parent | 60f178db65ca2a804da0cb887bf1d6d737b8235f (diff) | |
| download | coreboot-1a621507098a16de167f2904aa2f9f23e9bff800.tar.gz coreboot-1a621507098a16de167f2904aa2f9f23e9bff800.tar.bz2 coreboot-1a621507098a16de167f2904aa2f9f23e9bff800.zip | |
soc/intel/tigerlake: Set power limits for Tiger Lake Y-SKU
Set power limits in devicetree for Tiger Lake Y-SKU based volteer
variant boards.
BUG=b:152639350
BRANCH=None
TEST=Built and tested power limits on volteer variant board.
Change-Id: If4f1226473b48365e5962df9fff29910c99007fc
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43607
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/tigerlake/chip.h')
| -rw-r--r-- | src/soc/intel/tigerlake/chip.h | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 59dab58bb834..3d910cee942f 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -23,9 +23,11 @@ #define MAX_HD_AUDIO_SSP_LINKS 6 /* The first two are for TGL-U */ -#define POWER_LIMITS_U_4_CORE 0 -#define POWER_LIMITS_U_2_CORE 1 -#define POWER_LIMITS_MAX 2 +#define POWER_LIMITS_U_2_CORE 0 +#define POWER_LIMITS_U_4_CORE 1 +#define POWER_LIMITS_Y_2_CORE 2 +#define POWER_LIMITS_Y_4_CORE 3 +#define POWER_LIMITS_MAX 4 /* * Enable External V1P05 Rail in: BIT0:S0i1/S0i2, |