summaryrefslogtreecommitdiffstats
path: root/src/soc/intel/tigerlake/chip.h
Commit message (Expand)AuthorAgeFilesLines
* soc/intel/tigerlake: Drop redundant PcieRpEnableNico Huber2024-02-191-1/+0
* soc/intel/tigerlake: Replace TcssD3ColdDisable with D3COLD_SUPPORTSean Rhodes2023-04-201-2/+0
* soc/intel/tigerlake: Use common gpio.h includeDinesh Gehlot2023-01-181-2/+1
* soc/intel/tigerlake: Fix setting `HyperThreading`Angel Pons2022-12-051-3/+0
* soc/intel/tigerlake: Expose In-Band ECC config to mainboardFrans Hendriks2022-08-071-0/+21
* soc/intel/tigerlake: Add enum for `DdiPortXConfig`Angel Pons2022-05-051-7/+9
* soc/intel/tgl: drop orphaned VR domains enumMichael Niewöhner2022-03-081-12/+0
* soc/intel/tgl: Replace dt `HeciEnabled` by `HECI1 disable` configSubrata Banik2022-01-141-4/+0
* soc/intel/tigerlake: add devicetree option PcieRpSlotImplementedMichael Niewöhner2022-01-141-0/+2
* soc/intel/tigerlake: Hook up DPTF device to devicetreeFelix Singer2021-12-091-2/+0
* soc/intel/tigerlake: Drop unused SataEnable settingFelix Singer2021-12-091-1/+0
* soc/intel/tigerlake: Hook up SMBus device to devicetreeFelix Singer2021-12-091-3/+0
* soc/intel: replace dt option PmTimerDisabled by KconfigMichael Niewöhner2021-10-121-1/+1
* soc/intel/tigerlake: Hook up GMA ACPI brightness controlsTim Crawford2021-10-071-0/+4
* soc/tigerlake: Make IO decode / enable register configurableSean Rhodes2021-10-011-0/+4
* soc/intel/tigerlake: Add TGL-H power limitsJeremy Soller2021-08-241-5/+9
* soc/intel/tigerlake: Allow devicetree to fill UPD related to TCSS OCNick Vaccaro2021-05-141-0/+2
* soc/intel/tgl,mb/google/volteer: Add API for Type-C aux bias padsTim Wawrzynczak2021-05-061-10/+8
* soc/intel/alderlake: rename CONFIG_MAX_PCIE_CLOCKS to CONFIG_MAX_PCIE_CLOCK_SRCRizwan Qureshi2021-04-211-2/+2
* intel/tigerlake: Add Acoustic featuresShaunak Saha2021-04-061-9/+8
* soc/intel/tgl: Add configurable value for PmcUsb2PhySusPgEnableDerek Huang2021-03-191-0/+2
* soc/intel/tigerlake: Add CNVi Bluetooth flag at devicetree entryCliff Huang2021-03-151-0/+3
* soc/intel: Retype `CnviBtAudioOffload` devicetree optionAngel Pons2021-03-031-4/+1
* soc/intel/tgl: Update S0ix enable mask based on SoC and mainboard designShreesh Chhabbi2021-02-101-0/+24
* soc/intel/tgl: Add configurable value for ConfigTdpLevelDerek Huang2021-02-031-0/+3
* soc/intel/common: Move L1_substates_control to pcie_rp.hEric Lai2021-01-181-6/+2
* soc/intel/tgl: Add configurable value for UsbTcPortEnBrandon Breitenstein2021-01-141-0/+7
* soc/intel: hook up new gpio device in the soc chipsMichael Niewöhner2020-12-301-0/+1
* soc/intel/tigerlake: Drop unreferenced devicetree settingsAngel Pons2020-12-141-2/+0
* soc/intel/tigerlake: Expose UPD to enable Precision Time MeasurementDuncan Laurie2020-11-201-0/+3
* soc/intel/*/chip: Remove unused devicetree entryPatrick Rudolph2020-11-091-1/+0
* mb/*,soc/intel: drop the obsolete dt option `speed_shift_enable`Michael Niewöhner2020-10-261-3/+0
* soc/intel/tigerlake: Add Acoustic featuresShaunak Saha2020-10-231-0/+53
* soc/intel/tigerlake: Configure FSP UPDs for minimum assertion widthsJamie Ryu2020-09-231-0/+53
* soc/intel/{cnl,icl,jsl,tgl}: Clean up chip.hSubrata Banik2020-09-141-2/+0
* soc/intel/tigerlake: Allow fine grained control of S0iX statesJes Klinke2020-08-171-0/+17
* soc/intel/tigerlake: Configure TCSS D3Hot and D3ColdJohn Zhao2020-07-291-2/+2
* src/soc/intel: Add include <types.h>Elyes HAOUAS2020-07-261-1/+1
* soc/intel/tigerlake: Set power limits for Tiger Lake Y-SKUSumeet R Pawnikar2020-07-251-3/+5
* soc/intel/tigerlake: Hook up SATA Port Enable DITO UPDsShaunak Saha2020-07-151-6/+17
* mainboard/intel/tglrvp: Remove unused PrmrrSize chip configSubrata Banik2020-07-091-10/+0
* soc/intel/tigerlake: Add CpuReplacementCheck to chip optionsJamie Ryu2020-06-301-0/+6
* soc/intel/tigerlake: Add CmdMirror option in chip.hDavid Wu2020-06-221-0/+3
* mb/google/volteer: Override power limits with SKU-specific limitsTim Wawrzynczak2020-06-221-1/+6
* soc/soch/intel/tigerlake: Integrate PCIe hot-plug config UPDWonkyu Kim2020-06-171-0/+1
* soc/intel/tigerlake: Add devicetree support to change PCH VR settingsVenkata Krishna Nimmagadda2020-06-121-0/+40
* soc/intel/tigerlake: Set FSPS UPD ITbtConnectTopologyTimeoutInMsJohn Zhao2020-06-091-0/+3
* soc/intel/tigerlake: Configure TcssDma0En and TcssDma1EnJohn Zhao2020-05-301-4/+0
* soc/intel/tigerlake: Remove MIPI clock setting from devicetreeSrinidhi N Kaushik2020-05-261-3/+0
* soc/intel/tigerlake: Delete unused configurationWonkyu Kim2020-05-261-6/+0
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-04 04:31:01 +0000