diff options
| author | Brandon Breitenstein <brandon.breitenstein@intel.com> | 2020-12-21 14:55:38 -0800 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-01-14 19:53:18 +0000 |
| commit | bf50c31184d457c24f66b339cd28f84cbdd4177f (patch) | |
| tree | 67bc6f38a11a727d0c425dc451693ea8757fa6e2 /src/soc/intel/tigerlake/chip.h | |
| parent | 02e0456a252f324114cd6fad349b56cc5e3ea570 (diff) | |
| download | coreboot-bf50c31184d457c24f66b339cd28f84cbdd4177f.tar.gz coreboot-bf50c31184d457c24f66b339cd28f84cbdd4177f.tar.bz2 coreboot-bf50c31184d457c24f66b339cd28f84cbdd4177f.zip | |
soc/intel/tgl: Add configurable value for UsbTcPortEn
As a requirement of TCSS this setting needs to be correctly set
to determine what Type-C ports are enabled on the platform. Without
this value correctly set there can be adverse effects on the other
TCSS specific values.
BUG=b:159151238
BRANCH=firmware-volteer-13672.B
TEST=Built image for Voxel and verified that S0ix cycles no longer
fail when the IomPortPad is set to 0
Change-Id: I6c5260cda71041439fe89d15bd3cafd4052ef1e7
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48813
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Diffstat (limited to 'src/soc/intel/tigerlake/chip.h')
| -rw-r--r-- | src/soc/intel/tigerlake/chip.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index f38330b988f3..86e77da97262 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -328,6 +328,13 @@ struct soc_intel_tigerlake_config { uint8_t TcssXdciEn; /* + * Specifies which Type-C Ports are enabled on the system + * each bit represents a port starting at 0 + * Example: set value to 0x3 for ports 0 and 1 to be enabled + */ + uint8_t UsbTcPortEn; + + /* * IOM Port Config * If a port orientation needs to be controlled by the SOC this setting must be * updated to reflect the correct GPIOs being used for the SOC port flipping. |