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| author | Nick Vaccaro <nvaccaro@google.com> | 2021-05-11 16:39:32 -0700 |
|---|---|---|
| committer | Nick Vaccaro <nvaccaro@google.com> | 2021-05-14 23:00:01 +0000 |
| commit | 4b3e06edf2b7c2d99912038589764d551bc00c6f (patch) | |
| tree | 3a04517ed77edd47084e6707582978c0ab193c32 /src/soc/intel/tigerlake/chip.h | |
| parent | 1b242b6618d4cbb80d5b4268ba2b39ae363d96f9 (diff) | |
| download | coreboot-4b3e06edf2b7c2d99912038589764d551bc00c6f.tar.gz coreboot-4b3e06edf2b7c2d99912038589764d551bc00c6f.tar.bz2 coreboot-4b3e06edf2b7c2d99912038589764d551bc00c6f.zip | |
soc/intel/tigerlake: Allow devicetree to fill UPD related to TCSS OC
We need to change OC pin for type C USB3 ports and it depends
on the board design. Allowing it to be filled by devicetree will
make it easier to change the mapping based on the board design.
BUG=b:184660529
TEST="emerge-volteer coreboot" compiles without error.
Change-Id: I5058a18b1f4d11701cebbba85734fbc279539e52
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54075
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/tigerlake/chip.h')
| -rw-r--r-- | src/soc/intel/tigerlake/chip.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index c0110938713c..cc12da4a1aad 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -177,6 +177,8 @@ struct soc_intel_tigerlake_config { uint16_t usb3_wake_enable_bitmap; /* PCH USB2 PHY Power Gating disable */ uint8_t usb2_phy_sus_pg_disable; + /* Program OC pins for TCSS */ + struct tcss_port_config tcss_ports[MAX_TYPE_C_PORTS]; /* * Acoustic Noise Mitigation |