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| author | Raul E Rangel <rrangel@chromium.org> | 2020-07-13 16:10:34 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-07-15 08:38:43 +0000 |
| commit | 742abd3daf6be57de2df5002b8985ad36884c959 (patch) | |
| tree | cdfae09c0acf514a7b26c5256742e88f32ed281e /src/soc/intel/tigerlake/chip.h | |
| parent | 1aa5cff70908a18b1bd0fd41b2e2ad7014cf9813 (diff) | |
| download | coreboot-742abd3daf6be57de2df5002b8985ad36884c959.tar.gz coreboot-742abd3daf6be57de2df5002b8985ad36884c959.tar.bz2 coreboot-742abd3daf6be57de2df5002b8985ad36884c959.zip | |
soc/amd/picasso/acpi: Delete unused and invalid OperationRegions
0xc50, 0xc52, 0xc6f don't exist on Picasso. The PCI config space
registers define SATA and OHCI which are at the wrong bus locations.
I just remove the whole section since it's not used. We never access the
PCIe Error region, or the PM2 region either.
BUG=b:153001807, b:154756391
TEST=Build Trembyle
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I98aee09770f1df9f553c94580c1ee00c06a9cec1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/tigerlake/chip.h')
0 files changed, 0 insertions, 0 deletions