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| author | Michael Niewöhner <foss@mniewoehner.de> | 2022-01-09 02:20:17 +0100 |
|---|---|---|
| committer | Paul Fagerburg <pfagerburg@chromium.org> | 2022-01-14 00:29:28 +0000 |
| commit | 9f0285b6fe46d6ec76faad0c099239c227e5caa1 (patch) | |
| tree | dd6b79bf9a2e8134342400d53dc91b36ee7753f6 /src/soc/intel/tigerlake/chip.h | |
| parent | 7a2bc06b121a978b7517230f7b8de2b5cc94c7e7 (diff) | |
| download | coreboot-9f0285b6fe46d6ec76faad0c099239c227e5caa1.tar.gz coreboot-9f0285b6fe46d6ec76faad0c099239c227e5caa1.tar.bz2 coreboot-9f0285b6fe46d6ec76faad0c099239c227e5caa1.zip | |
soc/intel/tgl: deduplicate the PCIe root port map
Make use of the helper introduced in the parent change to deduplicate
the PCIe root port table.
Change-Id: I2dae4e4caf0a7ba3662889f3b31da0c3c299bc92
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel/tigerlake/chip.h')
0 files changed, 0 insertions, 0 deletions