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| author | Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> | 2020-05-15 15:55:37 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-20 09:14:11 +0000 |
| commit | d2132469ae86d7287576a2ba3211cdbfeb572703 (patch) | |
| tree | 2f9ccb52774aba1a0e0f9a2d85b59d52a5d1d9c0 /src/soc/intel/tigerlake/chip.h | |
| parent | 425d8640fa3d8e4a43bd9f2cc8f8fd7fedf675c3 (diff) | |
| download | coreboot-d2132469ae86d7287576a2ba3211cdbfeb572703.tar.gz coreboot-d2132469ae86d7287576a2ba3211cdbfeb572703.tar.bz2 coreboot-d2132469ae86d7287576a2ba3211cdbfeb572703.zip | |
tigerlake: update processor power limits configuration
Update processor power limit configuration parameters based on
common code base support for Intel Tigerlake SoC based platforms.
BRANCH=None
BUG=None
TEST=Built and tested on volteer system
Change-Id: Iccd387d78bb45ca3de73f531a901d1d3f793d7bd
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39345
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/tigerlake/chip.h')
| -rw-r--r-- | src/soc/intel/tigerlake/chip.h | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index a32cebe594dc..2e3591f4a650 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -7,6 +7,7 @@ #include <intelblocks/cfg.h> #include <intelblocks/gpio.h> #include <intelblocks/gspi.h> +#include <intelblocks/power_limit.h> #include <soc/gpe.h> #include <soc/gpio.h> #include <soc/gpio_defs.h> @@ -26,6 +27,9 @@ struct soc_intel_tigerlake_config { /* Common struct containing soc config data required by common code */ struct soc_intel_common_config common_soc_config; + /* Common struct containing power limits configuration information */ + struct soc_power_limits_config power_limits_config; + /* Gpio group routed to each dword of the GPE0 block. Values are * of the form PMC_GPP_[A:U] or GPD. */ uint8_t pmc_gpe0_dw0; /* GPE0_31_0 STS/EN */ @@ -144,8 +148,7 @@ struct soc_intel_tigerlake_config { /* HeciEnabled decides the state of Heci1 at end of boot * Setting to 0 (default) disables Heci1 and hides the device from OS */ uint8_t HeciEnabled; - /* PL2 Override value in Watts */ - uint32_t tdp_pl2_override; + /* Intel Speed Shift Technology */ uint8_t speed_shift_enable; |