diff options
| author | Aamir Bohra <aamir.bohra@intel.com> | 2020-03-23 10:13:10 +0530 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2020-04-01 19:12:30 +0000 |
| commit | 555c9b6268febf001e887fbb9e3c3f0901a371ac (patch) | |
| tree | d3b1968356086c05ac0894115f45b06cb8437e85 /src/soc/intel/tigerlake/include/soc/pci_devs.h | |
| parent | a23e0c9d74b7f06738ebf28b068e1bd63f246982 (diff) | |
| download | coreboot-555c9b6268febf001e887fbb9e3c3f0901a371ac.tar.gz coreboot-555c9b6268febf001e887fbb9e3c3f0901a371ac.tar.bz2 coreboot-555c9b6268febf001e887fbb9e3c3f0901a371ac.zip | |
soc/intel/tigerlake: Remove Jasper Lake SoC references
This implementation removes all JSL references from the TGL SoC code.
Additionally, mainboard code changes are done to support build.
BUG=b:150217037
TEST=build tglrvp and volteer
Change-Id: I18853aba8b1e6ff7d37c03e8dae2521719c7c727
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/tigerlake/include/soc/pci_devs.h')
| -rw-r--r-- | src/soc/intel/tigerlake/include/soc/pci_devs.h | 11 |
1 files changed, 0 insertions, 11 deletions
diff --git a/src/soc/intel/tigerlake/include/soc/pci_devs.h b/src/soc/intel/tigerlake/include/soc/pci_devs.h index f7ecc3fabd65..255081077add 100644 --- a/src/soc/intel/tigerlake/include/soc/pci_devs.h +++ b/src/soc/intel/tigerlake/include/soc/pci_devs.h @@ -89,11 +89,6 @@ #define PCH_DEV_SRAM _PCH_DEV(XHCI, 2) #define PCH_DEV_CNVI_WIFI _PCH_DEV(XHCI, 3) -#if CONFIG(SOC_INTEL_JASPERLAKE) -#define PCH_DEVFN_SDCARD _PCH_DEVFN(XHCI, 5) -#define PCH_DEV_SDCARD _PCH_DEV(XHCI, 5) -#endif - #define PCH_DEV_SLOT_SIO3 0x15 #define PCH_DEVFN_I2C0 _PCH_DEVFN(SIO3, 0) #define PCH_DEVFN_I2C1 _PCH_DEVFN(SIO3, 1) @@ -130,12 +125,6 @@ #define PCH_DEV_I2C5 _PCH_DEV(SIO4, 1) #define PCH_DEV_UART2 _PCH_DEV(SIO4, 2) -#if CONFIG(SOC_INTEL_JASPERLAKE) -#define PCH_DEV_SLOT_STORAGE 0x1a -#define PCH_DEVFN_EMMC _PCH_DEVFN(STORAGE, 0) -#define PCH_DEV_EMMC _PCH_DEV(STORAGE, 0) -#endif - #define PCH_DEV_SLOT_PCIE 0x1c #define PCH_DEVFN_PCIE1 _PCH_DEVFN(PCIE, 0) #define PCH_DEVFN_PCIE2 _PCH_DEVFN(PCIE, 1) |