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path: root/src/soc/intel/tigerlake/include/soc/pci_devs.h
Commit message (Expand)AuthorAgeFilesLines
* soc/intel/{adl,jsl,mtl,tgl}: Add ACPI name for GNA deviceMatt DeVillier2023-09-011-0/+4
* soc/intel/tigerlake: Add USBOTG and CrashLog to irq tableFrans Hendriks2022-08-101-0/+1
* soc/intel/tigerlake: Drop unused `PCH_DEV_SLOT_LPC` macroSubrata Banik2022-05-251-1/+0
* soc/intel/tigerlake: Add TGL-H PEG portsJeremy Soller2021-08-241-0/+5
* soc/intel/tigerlake: Add PCIe root ports for PCH-HJeremy Soller2021-08-241-0/+26
* soc/intel/tigerlake: Enable support for common IRQ blockTim Wawrzynczak2021-06-291-0/+1
* soc/intel/tigerlake: Remove obsolete CNVi Bluetooth PCI deviceCliff Huang2021-03-151-2/+0
* soc/intel/tigerlake: Add CrashLog implementation for intel TGLFrancois Toguo2021-02-221-0/+7
* soc/intel/tigerlake: Add some helper macros for accessing TCSS DMA devicesTim Wawrzynczak2020-11-301-2/+4
* soc/intel/tigerlake: Disable CPU PCIe in FSPShaunak Saha2020-07-261-0/+3
* soc/intel/tigerlake: Disable Thunderbolt PCIe root ports bus masterJohn Zhao2020-07-071-0/+2
* soc/intel/tigerlake: Disable VMDWonkyu Kim2020-05-261-0/+4
* soc/intel/tigerlake: Add FSP UPD TcssDma0En and TcssDma1EnJohn Zhao2020-05-181-3/+13
* treewide: Remove "this file is part of" linesPatrick Georgi2020-05-111-1/+0
* soc/intel/tigerlake: Use SPDX for GPL-2.0-only filesAngel Pons2020-04-061-13/+2
* soc/intel/tigerlake: Remove Jasper Lake SoC referencesAamir Bohra2020-04-011-11/+0
* soc/intel/tigerlake: Make PCH_DEV_UART3 macro definition properSubrata Banik2020-03-211-1/+1
* soc: Remove copyright noticesPatrick Georgi2020-03-181-1/+0
* soc/intel/tigerlake: Enable VT-d and generate DMAR ACPI tableJohn Zhao2020-03-121-1/+5
* soc/intel/tigerlake: Update FSP params for Jasper LakeMaulik V Vaghela2020-02-271-0/+11
* soc/intel/tigerlake: Update pci dev definitionWonkyu Kim2020-01-181-74/+64
* soc/intel/tigerlake/bootblock: Do initial SoC commit till bootblockSubrata Banik2019-11-091-0/+205
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