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| author | Subrata Banik <subratabanik@google.com> | 2022-05-23 12:07:32 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2022-05-25 18:08:06 +0000 |
| commit | 6299cecb0d6a23e5ed0a8257baef5e6d354de997 (patch) | |
| tree | 03022b0fe628511085670fae0460dfb4403470af /src/soc/intel/tigerlake/include/soc/pci_devs.h | |
| parent | f4ba356420790f463f39de10ec71f9a50c5eac12 (diff) | |
| download | coreboot-6299cecb0d6a23e5ed0a8257baef5e6d354de997.tar.gz coreboot-6299cecb0d6a23e5ed0a8257baef5e6d354de997.tar.bz2 coreboot-6299cecb0d6a23e5ed0a8257baef5e6d354de997.zip | |
soc/intel/tigerlake: Drop unused `PCH_DEV_SLOT_LPC` macro
This patch drops the unused `PCH_DEV_SLOT_LPC` macro from the
Tiger Lake SoC PCI device list.
BUG=none
TEST=Able to build and boot volteer, google board.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I27a2f31aa706c4d76e9f0db202422bc129368959
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Diffstat (limited to 'src/soc/intel/tigerlake/include/soc/pci_devs.h')
| -rw-r--r-- | src/soc/intel/tigerlake/include/soc/pci_devs.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/soc/intel/tigerlake/include/soc/pci_devs.h b/src/soc/intel/tigerlake/include/soc/pci_devs.h index eee03f980d72..05d96e8de7a3 100644 --- a/src/soc/intel/tigerlake/include/soc/pci_devs.h +++ b/src/soc/intel/tigerlake/include/soc/pci_devs.h @@ -210,7 +210,6 @@ #define PCH_DEV_GSPI1 _PCH_DEV(SIO5, 3) #define PCH_DEV_SLOT_ESPI 0x1f -#define PCH_DEV_SLOT_LPC PCH_DEV_SLOT_ESPI #define PCH_DEVFN_ESPI _PCH_DEVFN(ESPI, 0) #define PCH_DEVFN_P2SB _PCH_DEVFN(ESPI, 1) #define PCH_DEVFN_PMC _PCH_DEVFN(ESPI, 2) |