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| author | Francois Toguo <francois.toguo.fotso@intel.com> | 2021-01-26 10:27:49 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-02-22 07:22:50 +0000 |
| commit | 15cbc3b5996ae64aff2e4741c4c3ec3d7f5cc1a7 (patch) | |
| tree | ec401d461fcbbace3194553db3953a4d80e8d332 /src/soc/intel/tigerlake/romstage | |
| parent | 619c60f94cc00251bfaedde4f1764e2f96dcdecd (diff) | |
| download | coreboot-15cbc3b5996ae64aff2e4741c4c3ec3d7f5cc1a7.tar.gz coreboot-15cbc3b5996ae64aff2e4741c4c3ec3d7f5cc1a7.tar.bz2 coreboot-15cbc3b5996ae64aff2e4741c4c3ec3d7f5cc1a7.zip | |
soc/intel/tigerlake: Add CrashLog implementation for intel TGL
CrashLog is a diagnostic feature for Intel TGL based platforms.
It is meant to capture the state of the platform before a crash.
The state of relevant registers is preserved across a warm reset.
BUG=None
TEST=CrashLog data generated, extracted, processed, decoded sucessfully on delbin.
Signed-off-by: Francois Toguo <francois.toguo.fotso@intel.com>
Change-Id: Ie3763cebcd1178709cc8597710bf062a30901809
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49943
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel/tigerlake/romstage')
| -rw-r--r-- | src/soc/intel/tigerlake/romstage/fsp_params.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c index 27630ec0a15d..ebcc7d4b8cf1 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -215,6 +215,12 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, /* Change TmeEnable UPD value according to INTEL_TME Kconfig */ m_cfg->TmeEnable = CONFIG(INTEL_TME); + + /* crashLog config */ + if (CONFIG(SOC_INTEL_CRASHLOG)) { + m_cfg->CpuCrashLogDevice = 1; + m_cfg->CpuCrashLogEnable = 1; + } } void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) |