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path: root/src/soc/intel/tigerlake/romstage
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* soc/intel/tigerlake: Drop redundant PcieRpEnableNico Huber2024-02-191-6/+3
* soc/intel: Rename Makefiles from .inc to .mkMartin Roth2024-01-241-0/+0
* cpu/intel: Move is_tme_supported() from soc/intel to cpu/intelJeremy Compostella2023-09-121-0/+1
* soc/intel: Add max memory speed into dimm infoEric Lai2023-06-151-1/+2
* soc/intel/tigerlake: Use common gpio.h includeDinesh Gehlot2023-01-181-1/+1
* soc/intel/tigerlake: Fix setting `HyperThreading`Angel Pons2022-12-051-3/+0
* soc/intel: Add node_num to dimm_info struct + adjust dimm_info_fillDavid Milosevic2022-11-171-1/+2
* soc/intel/tigerlake: Clean up includesElyes Haouas2022-10-251-0/+1
* soc/intel: Enable TME based on supported CPU SKU and config optionSubrata Banik2022-08-211-2/+1
* soc/intel/tigerlake: Expose In-Band ECC config to mainboardFrans Hendriks2022-08-071-0/+16
* soc/intel: Rename heci_init to cse_initSubrata Banik2022-06-041-1/+1
* soc/intel/tigerlake: Hook up FSP hyper-threading setting to option APIFelix Singer2022-05-261-0/+3
* soc/intel/tigerlake: Hook up SMBus device to devicetreeFelix Singer2021-12-091-1/+1
* soc/intel/tigerlake: Set UserBd to recommended default for PCH-HJeremy Soller2021-08-241-1/+4
* soc/intel/tigerlake: Add TGL-H PEG portsJeremy Soller2021-08-241-1/+8
* soc/intel/tigerlake: Add PCH-H GPIO definitionsJeremy Soller2021-08-241-1/+1
* soc/intel/tigerlake: Make use of `cpu/intel/cpu_ids.h'Subrata Banik2021-07-171-1/+1
* soc/intel/tigerlake: Use `is_devfn_enabled()` for Crashlog UPDsSubrata Banik2021-07-151-4/+2
* soc/intel/tigerlake: Make use of is_devfn_enabled() functionSubrata Banik2021-06-161-32/+12
* soc/intel/alderlake: rename CONFIG_MAX_PCIE_CLOCKS to CONFIG_MAX_PCIE_CLOCK_SRCRizwan Qureshi2021-04-211-1/+1
* soc/intel: Drop `romstage_pch_init()` functionAngel Pons2021-03-013-13/+3
* soc/intel/tigerlake: Add CrashLog implementation for intel TGLFrancois Toguo2021-02-221-0/+6
* soc/intel/tigerlake: Disable Internal Gfx based on SOC_INTEL_DISABLE_IGDBora Guvendik2021-01-251-5/+6
* soc/intel/tigerlake: Enable CSE Lite driver for TGL platform in romstageSridhar Siricilla2020-12-141-1/+12
* soc/intel: remove duplicate weak versions of mainboard_get_dram_part_num()Nick Vaccaro2020-10-051-6/+0
* mb, soc: change mainboard_get_dram_part_num() prototypeNick Vaccaro2020-10-051-5/+8
* soc/intel/tigerlake: Set TME upd param based on configPratik Prajapati2020-09-301-0/+3
* soc/intel: rename get_prmrr_sizeMichael Niewöhner2020-09-211-1/+1
* soc/intel/tigerlake: Skip GPIO configuration from FSPSrinidhi N Kaushik2020-09-081-0/+3
* soc/intel/tigerlake: Rename pch_init() codeAlexey Buyanov2020-08-262-2/+2
* soc/intel/tigerlake: Fix IPU and Vtd configRavi Sarawadi2020-08-241-4/+15
* soc/intel/tigerlake: Simplify is-device-enabled checksFelix Singer2020-07-281-42/+18
* soc/intel/tigerlake: Disable CPU PCIe in FSPShaunak Saha2020-07-261-0/+4
* soc/intel/tigerlake: Disable VT-d and no DMAR table for pre-QS platformJohn Zhao2020-07-261-13/+27
* soc/intel/tigerlake: Move tco_configure to bootblockTim Wawrzynczak2020-07-121-4/+0
* mainboard/intel/tglrvp: Remove unused PrmrrSize chip configSubrata Banik2020-07-091-1/+2
* soc/intel/tigerlake: Add CpuReplacementCheck to chip optionsJamie Ryu2020-06-301-0/+3
* soc/intel/tigerlake: Add CmdMirror option in chip.hDavid Wu2020-06-221-0/+3
* soc/intel/tigerlake: Configure TcssDma0En and TcssDma1EnJohn Zhao2020-05-301-2/+11
* soc/intel/tigerlake: Add FSP UPD TcssDma0En and TcssDma1EnJohn Zhao2020-05-181-1/+5
* soc/intel/tigerlake: Add PchHdaIDispCodecDisconnect overrideEric Lai2020-05-181-0/+1
* src: Remove leading blank lines from SPDX headerElyes HAOUAS2020-05-181-3/+0
* treewide: Remove "this file is part of" linesPatrick Georgi2020-05-115-5/+0
* src/: Replace GPL boilerplate with SPDX headersPatrick Georgi2020-05-091-9/+1
* src/soc/tigerlake: Update SerialIoDebugMode UPD in FSP-MSrinidhi N Kaushik2020-05-041-0/+1
* soc/intel/{jsl,tgl}: Rename PcdDebugInterfaceFlags macros for better understa...Subrata Banik2020-05-011-1/+1
* soc/intel/tigerlake: Update iDisp Link UPD settingsSrinidhi N Kaushik2020-04-201-3/+0
* soc/intel/tigerlake: Merge the recent change from other platformsWonkyu Kim2020-04-201-16/+22
* soc/intel/tigerlake: Allow mainboard to override DRAM part numberMarco Chen2020-04-071-2/+23
* soc/intel/tigerlake: Use SPDX for GPL-2.0-only filesAngel Pons2020-04-064-52/+8
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