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| author | Nico Huber <nico.h@gmx.de> | 2024-01-12 16:22:19 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-02-19 13:19:26 +0000 |
| commit | 2bc4b934c35ca14ab1243c19dc6fa27688feefdb (patch) | |
| tree | 616e44e74f59f63376dbd7f3b5febbd31d02262c /src/soc/intel/tigerlake/romstage | |
| parent | 3d80d14cd4ed82e74057cea884dcb9bb7588c076 (diff) | |
| download | coreboot-2bc4b934c35ca14ab1243c19dc6fa27688feefdb.tar.gz coreboot-2bc4b934c35ca14ab1243c19dc6fa27688feefdb.tar.bz2 coreboot-2bc4b934c35ca14ab1243c19dc6fa27688feefdb.zip | |
soc/intel/tigerlake: Drop redundant PcieRpEnable
The PcieRpEnable option is redundant to our on/off setting in the
devicetrees. Let's use the common coreboot infrastructure instead.
Thanks to Nicholas for doing all the mainboard legwork!
Change-Id: Iacfef5f032278919f1fcf49e31fa42bcbf1eaf20
Signed-off-by: Nico Huber <nico.h@gmx.de>
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79920
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/tigerlake/romstage')
| -rw-r--r-- | src/soc/intel/tigerlake/romstage/fsp_params.c | 9 |
1 files changed, 3 insertions, 6 deletions
diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c index afcbf2f7117c..baf2eb36cfd8 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -9,6 +9,7 @@ #include <fsp/util.h> #include <gpio.h> #include <intelblocks/cpulib.h> +#include <intelblocks/pcie_rp.h> #include <option.h> #include <soc/iomap.h> #include <soc/msr.h> @@ -21,7 +22,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const struct soc_intel_tigerlake_config *config) { unsigned int i; - uint32_t cpu_id, mask = 0; + uint32_t cpu_id; m_cfg->HyperThreading = get_uint_option("hyper_threading", CONFIG(FSP_HYPERTHREADING)); @@ -49,11 +50,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, m_cfg->CpuRatio = (flex_ratio.lo >> 8) & 0xff; } - for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) { - if (config->PcieRpEnable[i]) - mask |= (1 << i); - } - m_cfg->PcieRpEnableMask = mask; + m_cfg->PcieRpEnableMask = pcie_rp_enable_mask(soc_get_pch_rp_groups()); memcpy(m_cfg->PcieClkSrcUsage, config->PcieClkSrcUsage, sizeof(config->PcieClkSrcUsage)); |