soc/intel/xeon_sp: Refactor code to allow for additional CPUs types

Refactor the code and split it into Xeon common and CPU-specific code.
Move most Skylake-SP code into skx/ and keep common code in the current
folder.

This is a preparation for future work that will enable next
generation server CPU.

TEST=Tested on OCP Tioga Pass. There does not seem to be degradation
of stability as far as I could tell.

Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Change-Id: I448e6cfd6a85efb83d132ad26565557fe55a265a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39601
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 63 insertions, 0 deletions

diff --git a/src/soc/intel/xeon_sp/bootblock.c b/src/soc/intel/xeon_sp/bootblock.c
new file mode 100644
index 000000000000..453c383897eb
--- /dev/null
+++ b/src/soc/intel/xeon_sp/bootblock.c
@@ -0,0 +1,63 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <bootblock_common.h>
+#include <device/pci.h>
+#include <FsptUpd.h>
+#include <intelblocks/fast_spi.h>
+#include <soc/iomap.h>
+#include <console/console.h>
+#include <cpu/x86/mtrr.h>
+#include <intelblocks/lpc_lib.h>
+
+const FSPT_UPD temp_ram_init_params = {
+	.FspUpdHeader = {
+		.Signature = FSPT_UPD_SIGNATURE,
+		.Revision = 1,
+		.Reserved = {0},
+	},
+	.FsptCoreUpd = {
+		.MicrocodeRegionBase = (UINT32)CONFIG_CPU_MICROCODE_CBFS_LOC,
+		.MicrocodeRegionLength = (UINT32)CONFIG_CPU_MICROCODE_CBFS_LEN,
+		.CodeRegionBase = (UINT32)CACHE_ROM_BASE,
+		.CodeRegionLength = (UINT32)CACHE_ROM_SIZE,
+		.Reserved1 = {0},
+	},
+	.FsptConfig = {
+		.PcdFsptPort80RouteDisable = 0,
+		.ReservedTempRamInitUpd = {0},
+	},
+	.UnusedUpdSpace0 = {0},
+	.UpdTerminator = 0x55AA,
+};
+
+asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
+{
+	fast_spi_cache_bios_region();
+
+	bootblock_main_with_basetime(base_timestamp);
+}
+
+void bootblock_soc_early_init(void)
+{
+	fast_spi_early_init(SPI_BASE_ADDRESS);
+	pch_enable_lpc();
+}
+
+void bootblock_soc_init(void)
+{
+	if (CONFIG(BOOTBLOCK_CONSOLE))
+		printk(BIOS_DEBUG, "FSP TempRamInit successful...\n");
+}