coreboot.git - Coreboot firmware sources

	Commit message (Expand)	Author	Age	Files	Lines
*	soc/intel/xeon_sp/bootblock: Fix out of order header files	Jeremy Compostella	2024-02-05	1	-6/+6
*	soc/intel/xeon_sp: Report platform cpu info	Naresh Solanki	2023-03-23	1	-0/+2
*	soc/intel/xeon_sp: select SCO_INTEL_COMMON_BLOCK_TCO	Johnny Lin	2023-01-08	1	-0/+4
*	pci_mmio_cfg: Always use pci_s_* functions	Nico Huber	2021-11-09	1	-3/+3
*	security/intel/cbnt: Add logging	Arthur Heymans	2021-06-21	1	-0/+5
*	soc/intel/xeon_sp: Remove superfluous printk	Arthur Heymans	2021-05-20	1	-3/+0
*	soc/intel/xeon_sp: Work around FSP-T not respecting its own API	Arthur Heymans	2020-11-22	1	-1/+14
*	soc/intel/xeon_sp/bootblock.c: Report the FSP-T output	Arthur Heymans	2020-11-02	1	-0/+3
*	vendorcode/intel/fsp/fsp2_0/cpx_sp: update to FSP WW20 release	Jonathan Zhang	2020-06-02	1	-1/+1
*	soc/intel/xeon_sp: Early programming of ACPI bar	Rocky Phagura	2020-06-02	1	-0/+2
*	treewide: Remove "this file is part of" lines	Patrick Georgi	2020-05-11	1	-1/+0
*	treewide: replace GPLv2 long form headers with SPDX header	Patrick Georgi	2020-05-06	1	-12/+1
*	treewide: Move "is part of the coreboot project" line in its own comment	Patrick Georgi	2020-05-06	1	-2/+1
*	soc/intel/xeon_sp: Configure P2SB BAR in bootblock	Andrey Petrov	2020-03-26	1	-0/+6
*	soc/intel/xeon_sp: Refactor code to allow for additional CPUs types	Andrey Petrov	2020-03-26	1	-0/+63