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| author | Arthur Heymans <arthur@aheymans.xyz> | 2021-05-12 16:22:05 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-06-21 05:42:00 +0000 |
| commit | ee55d71c96d44dc966abfa155e2178569ddb6b02 (patch) | |
| tree | 16ceef1b29044bac07cc499fa7acd136b8003a85 /src/soc/intel/xeon_sp/bootblock.c | |
| parent | 773ecfe11d27c9e2d6506400368be39db1e19bf5 (diff) | |
| download | coreboot-ee55d71c96d44dc966abfa155e2178569ddb6b02.tar.gz coreboot-ee55d71c96d44dc966abfa155e2178569ddb6b02.tar.bz2 coreboot-ee55d71c96d44dc966abfa155e2178569ddb6b02.zip | |
security/intel/cbnt: Add logging
This decodes and logs the CBnT status and error registers.
Change-Id: I8b57132bedbd944b9861ab0e2e0d14723cb61635
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54093
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/xeon_sp/bootblock.c')
| -rw-r--r-- | src/soc/intel/xeon_sp/bootblock.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/soc/intel/xeon_sp/bootblock.c b/src/soc/intel/xeon_sp/bootblock.c index 0b04f03215fe..1d706fe9c936 100644 --- a/src/soc/intel/xeon_sp/bootblock.c +++ b/src/soc/intel/xeon_sp/bootblock.c @@ -8,6 +8,7 @@ #include <console/console.h> #include <cpu/x86/mtrr.h> #include <intelblocks/lpc_lib.h> +#include <security/intel/cbnt/cbnt.h> #include <soc/pci_devs.h> #include <soc/bootblock.h> #include <fsp/util.h> @@ -67,5 +68,9 @@ void bootblock_soc_init(void) if (CONFIG(FSP_CAR)) report_fspt_output(); + + if (CONFIG(INTEL_CBNT_LOGGING)) + intel_cbnt_log_registers(); + bootblock_pch_init(); } |