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| author | Andrey Petrov <anpetrov@fb.com> | 2020-04-30 13:36:38 -0700 |
|---|---|---|
| committer | Andrey Petrov <andrey.petrov@gmail.com> | 2020-05-01 23:12:02 +0000 |
| commit | cf270f0d62dbe2647a8e4b80d6c986a6922d47f9 (patch) | |
| tree | c842a7b5824334a057f3c5cee27ee061127e2ed6 /src/soc/intel/xeon_sp/cpx/Kconfig | |
| parent | 15070e7ea86eefc211718b967e50fe44281bd879 (diff) | |
| download | coreboot-cf270f0d62dbe2647a8e4b80d6c986a6922d47f9.tar.gz coreboot-cf270f0d62dbe2647a8e4b80d6c986a6922d47f9.tar.bz2 coreboot-cf270f0d62dbe2647a8e4b80d6c986a6922d47f9.zip | |
soc/intel/xeon_sp/cpx: Enable common P2SB
Use common P2SB driver. This is needed to address a problem when
enumerator does not see p2sb device (since it is hidden) but it
is active and BAR is decoded.
Change-Id: I9cb821a5684f15f1e1486872bf806a6ee3d0676f
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40920
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/xeon_sp/cpx/Kconfig')
| -rw-r--r-- | src/soc/intel/xeon_sp/cpx/Kconfig | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig index 92681f276751..15669d182717 100644 --- a/src/soc/intel/xeon_sp/cpx/Kconfig +++ b/src/soc/intel/xeon_sp/cpx/Kconfig @@ -74,4 +74,7 @@ config FSP_TEMP_RAM_SIZE Refer to Platform FSP integration guide document to know the exact FSP requirement for Heap setup. +config SOC_INTEL_COMMON_BLOCK_P2SB + def_bool y + endif |