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| author | Andrey Petrov <anpetrov@fb.com> | 2020-04-20 18:07:08 -0700 |
|---|---|---|
| committer | Andrey Petrov <andrey.petrov@gmail.com> | 2020-04-24 19:44:00 +0000 |
| commit | dddb9a85bd1e9810410f14010f20c9ce2dabfee5 (patch) | |
| tree | edc0f2328984b41c2a0f15a414158850b10ebc41 /src/soc/intel/xeon_sp/cpx/Kconfig | |
| parent | 2f96970e1f4e586a4c5928fefab1bc0f98bc1351 (diff) | |
| download | coreboot-dddb9a85bd1e9810410f14010f20c9ce2dabfee5.tar.gz coreboot-dddb9a85bd1e9810410f14010f20c9ce2dabfee5.tar.bz2 coreboot-dddb9a85bd1e9810410f14010f20c9ce2dabfee5.zip | |
soc/intel/xeon_sp/cpx: Work around FSP-M issues
Currently FSP-M does not implement the spec completely, e.g it is unable
to use user-provided heap location in CAR. While this is being resolved,
this workaround is a stop-gap solution that allows multi-socket usage.
TEST=tested on OCP Sonora Pass EVT and Intel Cedar Island CRB
Change-Id: Ia2529526a8724cf54377b0bd2339b04fa900815a
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40555
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/xeon_sp/cpx/Kconfig')
| -rw-r--r-- | src/soc/intel/xeon_sp/cpx/Kconfig | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig index 70703d0c7856..88b0d5d65199 100644 --- a/src/soc/intel/xeon_sp/cpx/Kconfig +++ b/src/soc/intel/xeon_sp/cpx/Kconfig @@ -16,7 +16,6 @@ config USE_FSP2_0_DRIVER select UDK_2015_BINDING select POSTCAR_CONSOLE select POSTCAR_STAGE - select FSP_USES_CB_STACK config FSP_HEADER_PATH string "Location of FSP headers" @@ -40,11 +39,11 @@ config PCR_BASE_ADDRESS # currently FSP hardcodes [0fe800000;fe930000] for its heap config DCACHE_RAM_BASE hex - default 0xfe930000 + default 0xfe9a0000 config DCACHE_RAM_SIZE hex - default 0xd0000 + default 0x60000 config DCACHE_BSP_STACK_SIZE hex |