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| author | Tim Chu <Tim.Chu@quantatw.com> | 2022-12-14 11:37:55 +0000 |
|---|---|---|
| committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2023-03-22 12:05:47 +0000 |
| commit | d5bd8d54a32143c7d126a406eec1c3bcbf0240f5 (patch) | |
| tree | e38b8fec51be409d62f2c302cf669e28f931907a /src/soc/intel/xeon_sp/include | |
| parent | 65b7219bd3383d7b92afa1f081d46531077e1c14 (diff) | |
| download | coreboot-d5bd8d54a32143c7d126a406eec1c3bcbf0240f5.tar.gz coreboot-d5bd8d54a32143c7d126a406eec1c3bcbf0240f5.tar.bz2 coreboot-d5bd8d54a32143c7d126a406eec1c3bcbf0240f5.zip | |
soc/intel/xeon_sp: Enable FSP_ERROR_INFO_HOB handling
After calling FSP MemoryInit API, if there is an error, some FSPs
(such as SPR-SP FSP) is capable of generating FSP_ERROR_INFO_HOB.
Check existence of such a HOB and handle it accordingly.
Change-Id: Icb5c31daa223ba6b06ba1b2de4f8808e0b27899e
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72505
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Diffstat (limited to 'src/soc/intel/xeon_sp/include')
| -rw-r--r-- | src/soc/intel/xeon_sp/include/soc/romstage.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/xeon_sp/include/soc/romstage.h b/src/soc/intel/xeon_sp/include/soc/romstage.h index a2adfed918f9..2fd8128918eb 100644 --- a/src/soc/intel/xeon_sp/include/soc/romstage.h +++ b/src/soc/intel/xeon_sp/include/soc/romstage.h @@ -10,5 +10,6 @@ void mainboard_memory_init_params(FSPM_UPD * mupd); void mainboard_rtc_failed(void); void save_dimm_info(void); void mainboard_ewl_check(void); +void mainboard_fsp_error_handle(void); #endif /* _SOC_ROMSTAGE_H_ */ |